From 7d066330e0c3d47a0ad9eae111e469611ec83f2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 15 May 2023 01:29:44 -0400 Subject: [PATCH] ac/surface: relax custom pitch requirements to any multiple of 256B on gfx10.3+ Reviewed-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/common/ac_surface.c | 15 ++++++++------- src/amd/common/ac_surface.h | 3 ++- src/amd/vulkan/radv_image.c | 5 +++-- src/gallium/drivers/radeonsi/si_texture.c | 1 + 4 files changed, 14 insertions(+), 10 deletions(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index ac7b95aa892..2e154f9433d 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -2995,20 +2995,21 @@ static uint32_t ac_surface_get_pitch_align(const struct radeon_info *info, } bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf, - unsigned num_mipmap_levels, uint64_t offset, unsigned pitch) + unsigned num_layers, unsigned num_mipmap_levels, + uint64_t offset, unsigned pitch) { if ((ac_surface_get_pitch_align(info, surf) - 1) & pitch) return false; - /* - * GFX10 and newer don't support custom strides. Furthermore, for - * multiple miplevels or compression data we'd really need to rerun - * addrlib to update all the fields in the surface. That, however, is a - * software limitation and could be relaxed later. + /* Require an equal pitch with metadata (DCC), mipmapping, non-linear layout (that could be + * relaxed), or when the chip is GFX10, which is the only generation that can't override + * the pitch. */ bool require_equal_pitch = surf->surf_size != surf->total_size || + num_layers != 1 || num_mipmap_levels != 1 || - info->gfx_level >= GFX10; + !surf->is_linear || + info->gfx_level == GFX10; if (info->gfx_level >= GFX9) { if (pitch) { diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index e1e117a1000..50764794947 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -438,7 +438,8 @@ void ac_surface_compute_umd_metadata(const struct radeon_info *info, struct rade bool include_tool_md); bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf, - unsigned num_mipmap_levels, uint64_t offset, unsigned pitch); + unsigned num_layers, unsigned num_mipmap_levels, + uint64_t offset, unsigned pitch); struct ac_modifier_options { bool dcc; /* Whether to allow DCC. */ diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index aadbd72ca29..46438c6ab7e 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1515,7 +1515,7 @@ radv_image_override_offset_stride(struct radv_device *device, struct radv_image uint64_t offset, uint32_t stride) { ac_surface_override_offset_stride(&device->physical_device->rad_info, &image->planes[0].surface, - image->vk.mip_levels, offset, stride); + image->vk.array_layers, image->vk.mip_levels, offset, stride); } static void @@ -1845,7 +1845,8 @@ radv_image_create_layout(struct radv_device *device, struct radv_image_create_in } if (!ac_surface_override_offset_stride(&device->physical_device->rad_info, - &image->planes[plane].surface, image->vk.mip_levels, + &image->planes[plane].surface, + image->vk.array_layers, image->vk.mip_levels, offset, stride)) return VK_ERROR_INVALID_DRM_FORMAT_MODIFIER_PLANE_LAYOUT_EXT; diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index b635a5e66e1..6846342ad7b 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -932,6 +932,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, tex->surface = *surface; if (!ac_surface_override_offset_stride(&sscreen->info, &tex->surface, + tex->buffer.b.b.array_size, tex->buffer.b.b.last_level + 1, offset, pitch_in_bytes / tex->surface.bpe)) goto error;