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intel/brw: Retype some regs to BRW_TYPE_UD for Xe2 indirect accesses

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Following https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28957,
some Xe2 code paths started triggering asserts.

In the cases fixed by this patch, it was because of the assert added
to brw_type_larger_of() in cf8ed9925f ("intel/brw: Make a helper for
finding the largest of two types"), and then brw_type_larger_of() is
used in 674e89953f. (For example, the assert was triggering when the
SHL types differed between D and UD.)

Fixes: 674e89953f ("intel/brw: Use new builder helpers that allocate a VGRF destination")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29925>
This commit is contained in:
Jordan Justen
2024-04-30 11:19:36 -07:00
committed by Marge Bot
parent 646a0ea576
commit 7b3149c99b
1 changed files with 6 additions and 3 deletions
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src/intel/compiler/brw_fs_nir.cpp
+6 -3
View File
@@ -2754,7 +2754,7 @@ get_indirect_offset(nir_to_brw_state &ntb, nir_intrinsic_instr *instr)
return offset;
/* Convert Owords (16-bytes) to bytes */
return ntb.bld.SHL(offset, brw_imm_ud(4u));
return ntb.bld.SHL(retype(offset, BRW_TYPE_UD), brw_imm_ud(4u));
}
static void
@@ -5545,7 +5545,8 @@ emit_urb_indirect_writes_xe2(const fs_builder &bld, nir_intrinsic_instr *instr,
payload_srcs[c] = horiz_offset(offset(src, bld, c), write_size * q);
fs_reg addr =
wbld.ADD(wbld.SHL(horiz_offset(offset_src, write_size * q),
wbld.ADD(wbld.SHL(retype(horiz_offset(offset_src, write_size * q),
BRW_TYPE_UD),
brw_imm_ud(2)), urb_handle);
fs_reg srcs[URB_LOGICAL_NUM_SRCS];
@@ -5789,7 +5790,9 @@ emit_urb_indirect_reads_xe2(const fs_builder &bld, nir_intrinsic_instr *instr,
for (unsigned q = 0; q < bld.dispatch_width() / 16; q++) {
fs_builder wbld = bld.group(16, q);
fs_reg addr = wbld.SHL(horiz_offset(offset_src, 16 * q), brw_imm_ud(2));
fs_reg addr = wbld.SHL(retype(horiz_offset(offset_src, 16 * q),
BRW_TYPE_UD),
brw_imm_ud(2));
fs_reg srcs[URB_LOGICAL_NUM_SRCS];
srcs[URB_LOGICAL_SRC_HANDLE] = wbld.ADD(addr, urb_handle);