AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

pan/genxml: Rework the RT/ZS emission logic

Browse Source 
For the ZS emission logic, we split the descriptor in 3 parts: ZS, S and
CRC, so we can easily mix and match each variant with pan_merge(). For
RTs, we just define a layout per variant instead of overlays, which makes
dumps less verbose, and avoid the situation where overlapping fields
get accidentally overwritten in the desc emission logic.

While at it, add the `Surface stride hi` fiels to the ZS/Color target
descriptors so we're all set to bump the image size limit.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Tested-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35731>
This commit is contained in:
Boris Brezillon
2025-06-23 12:58:29 +02:00
committed by Marge Bot
parent 61d6e92f25
commit 7a763bb0a3
9 changed files with 1455 additions and 512 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/panfrost/genxml/decode.c
+129 -14
View File
@@ -72,24 +72,142 @@ pandecode_midgard_tiler_descriptor(struct pandecode_context *ctx,
#if PAN_ARCH >= 5
static void
pandecode_render_target(struct pandecode_context *ctx, uint64_t gpu_va,
unsigned gpu_id,
const struct MALI_FRAMEBUFFER_PARAMETERS *fb)
pandecode_rt(struct pandecode_context *ctx, unsigned index, uint64_t gpu_va)
{
uint64_t rt_va = gpu_va + index * pan_size(RENDER_TARGET);
const struct mali_render_target_packed *PANDECODE_PTR_VAR(ctx, rtp, rt_va);
pan_unpack(rtp, RENDER_TARGET, rt);
#if PAN_ARCH >= 10
switch (rt.rgb.writeback_mode) {
case MALI_WRITEBACK_MODE_COMPAT:
break;
case MALI_WRITEBACK_MODE_AFRC_RGB:
DUMP_UNPACKED(ctx, AFRC_RGB_RENDER_TARGET, rt.afrc_rgb,
"AFRC RGB Color Render Target %d:\n", index);
break;
case MALI_WRITEBACK_MODE_AFRC_YUV:
DUMP_UNPACKED(ctx, AFRC_YUV_RENDER_TARGET, rt.afrc_yuv,
"AFRC YUV Color Render Target %d:\n", index);
break;
default:
unreachable("Invalid writeback mode");
}
#endif
switch (rt.rgb.writeback_block_format) {
#if PAN_ARCH >= 7
case MALI_BLOCK_FORMAT_NO_WRITE:
#else
case MALI_BLOCK_FORMAT_TILED_LINEAR:
#endif
case MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED:
case MALI_BLOCK_FORMAT_LINEAR:
if (rt.rgb.yuv_enable) {
DUMP_UNPACKED(ctx, YUV_RENDER_TARGET, rt.yuv,
"%s YUV Color Render Target %d:\n",
rt.rgb.writeback_block_format == MALI_BLOCK_FORMAT_LINEAR
? "Linear"
: "U-Tiled",
index);
} else {
DUMP_UNPACKED(ctx, RGB_RENDER_TARGET, rt.rgb,
"%s RGB Color Render Target %d:\n",
rt.rgb.writeback_block_format == MALI_BLOCK_FORMAT_LINEAR
? "Linear"
: "U-Tiled",
index);
}
break;
#if PAN_ARCH >= 7
case MALI_BLOCK_FORMAT_AFBC_TILED:
#endif
case MALI_BLOCK_FORMAT_AFBC:
#if PAN_ARCH >= 6
if (rt.rgb.yuv_enable) {
DUMP_UNPACKED(ctx, AFBC_YUV_RENDER_TARGET, rt.afbc_yuv,
"AFBC YUV Color Render Target %d:\n", index);
break;
}
#else
assert(!rt.rgb.yuv_enable);
#endif
DUMP_UNPACKED(ctx, AFBC_RGB_RENDER_TARGET, rt.afbc_rgb,
"AFBC RGB Color Render Target %d:\n", index);
break;
}
}
static void
pandecode_rts(struct pandecode_context *ctx, uint64_t gpu_va, unsigned gpu_id,
const struct MALI_FRAMEBUFFER_PARAMETERS *fb)
{
pandecode_log(ctx, "Color Render Targets @%" PRIx64 ":\n", gpu_va);
ctx->indent++;
for (int i = 0; i < (fb->render_target_count); i++) {
uint64_t rt_va = gpu_va + i * pan_size(RENDER_TARGET);
const struct mali_render_target_packed *PANDECODE_PTR_VAR(
ctx, rtp, (uint64_t)rt_va);
DUMP_CL(ctx, RENDER_TARGET, rtp, "Color Render Target %d:\n", i);
}
for (int i = 0; i < (fb->render_target_count); i++)
pandecode_rt(ctx, i, gpu_va);
ctx->indent--;
pandecode_log(ctx, "\n");
}
static void
pandecode_zs_crc_ext(struct pandecode_context *ctx, uint64_t gpu_va)
{
const struct mali_zs_crc_extension_packed *PANDECODE_PTR_VAR(
ctx, zs_crc_packed, (uint64_t)gpu_va);
pan_unpack(zs_crc_packed, ZS_CRC_EXTENSION, zs_crc);
DUMP_UNPACKED(ctx, CRC, zs_crc.crc, "CRC:\n");
switch (zs_crc.zs.block_format) {
#if PAN_ARCH >= 7
case MALI_BLOCK_FORMAT_NO_WRITE:
#else
case MALI_BLOCK_FORMAT_TILED_LINEAR:
#endif
case MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED:
case MALI_BLOCK_FORMAT_LINEAR:
DUMP_UNPACKED(ctx, ZS_TARGET, zs_crc.zs, "ZS:\n");
break;
#if PAN_ARCH >= 7
case MALI_BLOCK_FORMAT_AFBC_TILED:
#endif
case MALI_BLOCK_FORMAT_AFBC:
DUMP_UNPACKED(ctx, AFBC_ZS_TARGET, zs_crc.afbc_zs, "ZS:\n");
break;
default:
unreachable("Invalid block format");
}
switch (zs_crc.s.block_format) {
#if PAN_ARCH >= 7
case MALI_BLOCK_FORMAT_NO_WRITE:
#else
case MALI_BLOCK_FORMAT_TILED_LINEAR:
#endif
case MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED:
case MALI_BLOCK_FORMAT_LINEAR:
DUMP_UNPACKED(ctx, S_TARGET, zs_crc.s, "S:\n");
break;
#if PAN_ARCH >= 9
case MALI_BLOCK_FORMAT_AFBC_TILED:
case MALI_BLOCK_FORMAT_AFBC:
DUMP_UNPACKED(ctx, AFBC_S_TARGET, zs_crc.afbc_s, "S:\n");
break;
#endif
default:
unreachable("Invalid block format");
}
pandecode_log(ctx, "\n");
}
#endif
#if PAN_ARCH >= 6
static void
@@ -175,16 +293,13 @@ GENX(pandecode_fbd)(struct pandecode_context *ctx, uint64_t gpu_va,
gpu_va += pan_size(FRAMEBUFFER);
if (params.has_zs_crc_extension) {
const struct mali_zs_crc_extension_packed *PANDECODE_PTR_VAR(
ctx, zs_crc, (uint64_t)gpu_va);
DUMP_CL(ctx, ZS_CRC_EXTENSION, zs_crc, "ZS CRC Extension:\n");
pandecode_log(ctx, "\n");
pandecode_zs_crc_ext(ctx, gpu_va);
gpu_va += pan_size(ZS_CRC_EXTENSION);
}
if (is_fragment)
pandecode_render_target(ctx, gpu_va, gpu_id, &params);
pandecode_rts(ctx, gpu_va, gpu_id, &params);
return (struct pandecode_fbd){
.rt_count = params.render_target_count,
src/panfrost/genxml/v10.xml
+192 -44
View File
@@ -1666,33 +1666,70 @@
<field name="Tiler" size="64" start="14:0" type="address"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="ZS Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="ZS Block Format" size="4" start="0:4" type="Block Format"/>
<field name="ZS MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="CRC Render Target" size="4" start="0:13" type="uint"/>
<field name="S Write Format" size="4" start="0:16" type="S Format"/>
<field name="S Block Format" size="4" start="0:20" type="Block Format"/>
<field name="S MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<struct name="CRC" align="64" size="16">
<field name="Render Target" size="3" start="0:13" type="uint"/>
<field name="Row Stride" size="32" start="1:0" type="uint"/>
<field name="Clear Color" size="64" start="2:0" type="hex"/>
<field name="Base" size="64" start="4:0" type="address"/>
</struct>
<field name="AFBC Reverse Issue Order" size="1" start="0:30" type="bool"/>
<struct name="ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="Block Format" size="4" start="0:4" type="Block Format"/>
<field name="MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Base" size="64" start="8:0" type="address"/>
<field name="Row Stride" size="32" start="10:0" type="uint"/>
<field name="Surface Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="AFBC ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="Block Format" size="4" start="0:4" type="Block Format"/>
<field name="MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="Reverse Issue Order" size="1" start="0:30" type="bool"/>
<!-- Note: Must be set if AFBC is enabled and effective_tile_size is not 16x16 -->
<field name="ZS Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="CRC Row Stride" size="32" start="1:0" type="uint"/>
<field name="CRC Clear Color" size="64" start="2:0" type="hex"/>
<field name="CRC Base" size="64" start="4:0" type="address"/>
<field name="ZS Writeback Base" size="64" start="8:0" type="address"/>
<field name="Header" size="64" start="8:0" type="address"/>
<!-- Header clumps per row (different than Bifrost's AFBC line stride) -->
<field name="ZS Writeback Row Stride" size="32" start="10:0" type="uint"/>
<field name="ZS Writeback Surface Stride" size="32" start="11:0" type="uint"/>
<field name="ZS AFBC Body Offset" size="32" start="11:0" type="uint"/>
<field name="Header Row Stride" size="32" start="10:0" type="uint"/>
<field name="Body Offset" size="32" start="11:0" type="uint"/>
</struct>
<field name="S Writeback Base" size="64" start="12:0" type="address"/>
<field name="S Writeback Row Stride" size="32" start="14:0" type="uint"/>
<field name="S Writeback Surface Stride" size="32" start="15:0" type="uint"/>
<field name="S AFBC Body Offset" size="32" start="15:0" type="uint"/>
<struct name="S Target" align="64" size="16">
<field name="Write Format" size="4" start="0:16" type="S Format"/>
<field name="Block Format" size="4" start="0:20" type="Block Format"/>
<field name="MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Base" size="64" start="12:0" type="address"/>
<field name="Row Stride" size="32" start="14:0" type="uint"/>
<field name="Surface Stride" size="32" start="15:0" type="uint"/>
</struct>
<struct name="AFBC S Target" align="64" size="16">
<field name="Write Format" size="4" start="0:16" type="S Format"/>
<field name="Block Format" size="4" start="0:20" type="Block Format"/>
<field name="MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<field name="Reverse Issue Order" size="1" start="0:30" type="bool"/>
<!-- Note: Must be set if AFBC is enabled and effective_tile_size is not 16x16 -->
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Header" size="64" start="12:0" type="address"/>
<field name="Header Row Stride" size="32" start="14:0" type="uint"/>
<field name="Body Offset" size="32" start="15:0" type="uint"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="CRC" size="512" start="0" type="CRC"/>
<field name="AFBC ZS" size="512" start="0" type="AFBC ZS Target"/>
<field name="ZS" size="512" start="0" type="ZS Target"/>
<field name="AFBC S" size="512" start="0" type="AFBC S Target"/>
<field name="S" size="512" start="0" type="S Target"/>
</struct>
<enum name="YUV Conv K6">
@@ -1712,8 +1749,46 @@
<value name="256" value="1"/>
</enum>
<struct name="Render Target YUV Overlay" size="16">
<field name="Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="RGB Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="YUV Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
@@ -1723,9 +1798,23 @@
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="32" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target AFBC Overlay" size="16">
<struct name="AFBC RGB Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Transform" size="1" start="2:0" type="bool"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
@@ -1737,28 +1826,13 @@
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="32" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target AFRC Overlay" size="16">
<field name="Writeback Format" size="8" start="1:0" type="Color Format"/>
<field name="Block Size" size="4" start="2:4" type="AFRC Block Size"/>
<field name="Format" size="8" start="2:8" type="AFRC Format"/>
</struct>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="Render Target" align="64">
<field name="YUV" size="512" start="0:0" type="Render Target YUV Overlay"/>
<field name="AFBC" size="512" start="0:0" type="Render Target AFBC Overlay"/>
<field name="AFRC" size="512" start="0:0" type="Render Target AFRC Overlay"/>
<struct name="AFBC YUV Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
@@ -1769,10 +1843,84 @@
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="RGB" size="128" start="8:0" type="RT Buffer"/>
<field name="YUV Transform" size="1" start="2:0" type="bool" default="false"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
<field name="Reverse issue order" size="1" start="2:3" type="bool"/>
<field name="Front buffer" size="1" start="2:4" type="bool"/>
<field name="Alpha hint" size="1" start="2:5" type="bool"/>
<field name="Compression mode" size="6" start="2:10" type="AFBC Compression Mode"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="32" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFRC RGB Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="AFRC RGB"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Writeback Format" size="8" start="1:0" type="Color Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="AFRC Block Size" size="4" start="2:4" type="AFRC Block Size"/>
<field name="AFRC Format" size="8" start="2:8" type="AFRC Format"/>
<field name="AFRC Codec args" size="8" start="3:0" type="uint"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFRC YUV Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="AFRC YUV"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Writeback Format" size="8" start="1:0" type="Color Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="AFRC Luma Block Size" size="4" start="2:4" type="AFRC Block Size"/>
<field name="AFRC Luma Format" size="8" start="2:8" type="AFRC Format"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="AFRC Luma codec args" size="8" start="3:0" type="uint"/>
<field name="AFRC Chroma codec args" size="8" start="3:8" type="uint"/>
<field name="AFRC Chroma Block Size" size="4" start="3:20" type="AFRC Block Size"/>
<field name="AFRC Chroma Format" size="8" start="3:24" type="AFRC Format"/>
<field name="Plane 0 Base" size="64" start="4:0" type="address"/>
<field name="Plane 1 Base" size="64" start="6:0" type="address"/>
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="32" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target" align="64">
<field name="RGB" size="512" start="0:0" type="RGB Render Target"/>
<field name="YUV" size="512" start="0:0" type="YUV Render Target"/>
<field name="AFBC RGB" size="512" start="0:0" type="AFBC RGB Render Target"/>
<field name="AFBC YUV" size="512" start="0:0" type="AFBC YUV Render Target"/>
<field name="AFRC RGB" size="512" start="0:0" type="AFRC RGB Render Target"/>
<field name="AFRC YUV" size="512" start="0:0" type="AFRC YUV Render Target"/>
</struct>
<enum name="Chunk Size">
<value name="256 KiB" value="0"/>
<value name="512 KiB" value="1"/>
src/panfrost/genxml/v12.xml
+213 -62
View File
@@ -1861,7 +1861,8 @@
<struct name="RT Buffer">
<field name="Base" size="64" start="0:0" type="address"/>
<field name="Row Stride" size="32" start="2:0" type="uint"/>
<field name="Row Stride" size="27" start="2:0" type="uint"/>
<field name="Surface Stride hi" size="5" start="2:27" type="uint"/>
<field name="Surface Stride" size="32" start="3:0" type="uint"/>
</struct>
@@ -1954,33 +1955,72 @@
<field name="VRS Image Plane" size="59" start="16:5" type="address"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="ZS Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="ZS Block Format" size="4" start="0:4" type="Block Format"/>
<field name="ZS MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="CRC Render Target" size="4" start="0:13" type="uint"/>
<field name="S Write Format" size="4" start="0:16" type="S Format"/>
<field name="S Block Format" size="4" start="0:20" type="Block Format"/>
<field name="S MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<struct name="CRC" align="64" size="16">
<field name="Render Target" size="3" start="0:13" type="uint"/>
<field name="Row Stride" size="27" start="1:0" type="uint"/>
<field name="Clear Color" size="64" start="2:0" type="hex"/>
<field name="Base" size="64" start="4:0" type="address"/>
</struct>
<field name="AFBC Reverse Issue Order" size="1" start="0:30" type="bool"/>
<struct name="ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="Block Format" size="4" start="0:4" type="Block Format"/>
<field name="MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Base" size="64" start="8:0" type="address"/>
<field name="Row Stride" size="27" start="10:0" type="uint"/>
<field name="Surface Stride hi" size="5" start="10:27" type="uint"/>
<field name="Surface Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="AFBC ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="Block Format" size="4" start="0:4" type="Block Format"/>
<field name="MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="Reverse Issue Order" size="1" start="0:30" type="bool"/>
<!-- Note: Must be set if AFBC is enabled and effective_tile_size is not 16x16 -->
<field name="ZS Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="CRC Row Stride" size="32" start="1:0" type="uint"/>
<field name="CRC Clear Color" size="64" start="2:0" type="hex"/>
<field name="CRC Base" size="64" start="4:0" type="address"/>
<field name="ZS Writeback Base" size="64" start="8:0" type="address"/>
<field name="Header" size="64" start="8:0" type="address"/>
<!-- Header clumps per row (different than Bifrost's AFBC line stride) -->
<field name="ZS Writeback Row Stride" size="32" start="10:0" type="uint"/>
<field name="ZS Writeback Surface Stride" size="32" start="11:0" type="uint"/>
<field name="ZS AFBC Body Offset" size="32" start="11:0" type="uint"/>
<field name="Header Row Stride" size="27" start="10:0" type="uint"/>
<field name="Body Offset" size="32" start="11:0" type="uint"/>
</struct>
<field name="S Writeback Base" size="64" start="12:0" type="address"/>
<field name="S Writeback Row Stride" size="32" start="14:0" type="uint"/>
<field name="S Writeback Surface Stride" size="32" start="15:0" type="uint"/>
<field name="S AFBC Body Offset" size="32" start="15:0" type="uint"/>
<struct name="S Target" align="64" size="16">
<field name="Write Format" size="4" start="0:16" type="S Format"/>
<field name="Block Format" size="4" start="0:20" type="Block Format"/>
<field name="MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Base" size="64" start="12:0" type="address"/>
<field name="Row Stride" size="27" start="14:0" type="uint"/>
<field name="Surface Stride hi" size="5" start="14:27" type="uint"/>
<field name="Surface Stride" size="32" start="15:0" type="uint"/>
</struct>
<struct name="AFBC S Target" align="64" size="16">
<field name="Write Format" size="4" start="0:16" type="S Format"/>
<field name="Block Format" size="4" start="0:20" type="Block Format"/>
<field name="MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<field name="Reverse Issue Order" size="1" start="0:30" type="bool"/>
<!-- Note: Must be set if AFBC is enabled and effective_tile_size is not 16x16 -->
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Header" size="64" start="12:0" type="address"/>
<field name="Header Row Stride" size="27" start="14:0" type="uint"/>
<field name="Body Offset" size="32" start="15:0" type="uint"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="CRC" size="512" start="0" type="CRC"/>
<field name="AFBC ZS" size="512" start="0" type="AFBC ZS Target"/>
<field name="ZS" size="512" start="0" type="ZS Target"/>
<field name="AFBC S" size="512" start="0" type="AFBC S Target"/>
<field name="S" size="512" start="0" type="S Target"/>
</struct>
<enum name="YUV Conv K6">
@@ -2000,39 +2040,6 @@
<value name="256" value="1"/>
</enum>
<struct name="Render Target YUV Overlay" size="16">
<field name="Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Plane 0 Base" size="64" start="4:0" type="address"/>
<field name="Plane 1 Base" size="64" start="6:0" type="address"/>
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="32" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="Render Target AFBC Overlay" size="16">
<field name="YUV Transform" size="1" start="2:0" type="bool"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
<field name="Reverse issue order" size="1" start="2:3" type="bool"/>
<field name="Front buffer" size="1" start="2:4" type="bool"/>
<field name="Alpha hint" size="1" start="2:5" type="bool"/>
<field name="Compression mode" size="6" start="2:10" type="AFBC Compression Mode"/>
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="32" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
</struct>
<struct name="Render Target AFRC Overlay" size="16">
<field name="Writeback Format" size="8" start="1:0" type="Color Format"/>
<field name="Block Size" size="4" start="2:4" type="AFRC Block Size"/>
<field name="Format" size="8" start="2:8" type="AFRC Format"/>
</struct>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
@@ -2040,13 +2047,10 @@
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="Render Target" align="64">
<field name="YUV" size="512" start="0:0" type="Render Target YUV Overlay"/>
<field name="AFBC" size="512" start="0:0" type="Render Target AFBC Overlay"/>
<field name="AFRC" size="512" start="0:0" type="Render Target AFRC Overlay"/>
<struct name="RGB Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
@@ -2057,10 +2061,157 @@
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="RGB" size="128" start="8:0" type="RT Buffer"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="YUV Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Plane 0 Base" size="64" start="4:0" type="address"/>
<field name="Plane 1 Base" size="64" start="6:0" type="address"/>
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="27" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="27" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFBC RGB Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Transform" size="1" start="2:0" type="bool"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
<field name="Reverse issue order" size="1" start="2:3" type="bool"/>
<field name="Front buffer" size="1" start="2:4" type="bool"/>
<field name="Alpha hint" size="1" start="2:5" type="bool"/>
<field name="Compression mode" size="6" start="2:10" type="AFBC Compression Mode"/>
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="27" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFBC YUV Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Transform" size="1" start="2:0" type="bool" default="false"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
<field name="Reverse issue order" size="1" start="2:3" type="bool"/>
<field name="Front buffer" size="1" start="2:4" type="bool"/>
<field name="Alpha hint" size="1" start="2:5" type="bool"/>
<field name="Compression mode" size="6" start="2:10" type="AFBC Compression Mode"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="27" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFRC RGB Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="AFRC RGB"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Writeback Format" size="8" start="1:0" type="Color Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="AFRC Block Size" size="4" start="2:4" type="AFRC Block Size"/>
<field name="AFRC Format" size="8" start="2:8" type="AFRC Format"/>
<field name="AFRC Codec args" size="8" start="3:0" type="uint"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFRC YUV Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="AFRC YUV"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Writeback Format" size="8" start="1:0" type="Color Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="AFRC Luma Block Size" size="4" start="2:4" type="AFRC Block Size"/>
<field name="AFRC Luma Format" size="8" start="2:8" type="AFRC Format"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="AFRC Luma codec args" size="8" start="3:0" type="uint"/>
<field name="AFRC Chroma codec args" size="8" start="3:8" type="uint"/>
<field name="AFRC Chroma Block Size" size="4" start="3:20" type="AFRC Block Size"/>
<field name="AFRC Chroma Format" size="8" start="3:24" type="AFRC Format"/>
<field name="Plane 0 Base" size="64" start="4:0" type="address"/>
<field name="Plane 1 Base" size="64" start="6:0" type="address"/>
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="27" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="27" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target" align="64">
<field name="RGB" size="512" start="0:0" type="RGB Render Target"/>
<field name="YUV" size="512" start="0:0" type="YUV Render Target"/>
<field name="AFBC RGB" size="512" start="0:0" type="AFBC RGB Render Target"/>
<field name="AFBC YUV" size="512" start="0:0" type="AFBC YUV Render Target"/>
<field name="AFRC RGB" size="512" start="0:0" type="AFRC RGB Render Target"/>
<field name="AFRC YUV" size="512" start="0:0" type="AFRC YUV Render Target"/>
</struct>
<enum name="Chunk Size">
<value name="256 KiB" value="0"/>
<value name="512 KiB" value="1"/>
src/panfrost/genxml/v13.xml
+213 -62
View File
@@ -2163,7 +2163,8 @@
<struct name="RT Buffer">
<field name="Base" size="64" start="0:0" type="address"/>
<field name="Row Stride" size="32" start="2:0" type="uint"/>
<field name="Row Stride" size="27" start="2:0" type="uint"/>
<field name="Surface Stride hi" size="5" start="2:27" type="uint"/>
<field name="Surface Stride" size="32" start="3:0" type="uint"/>
</struct>
@@ -2260,33 +2261,72 @@
<field name="VRS Image Plane" size="59" start="16:5" type="address"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="ZS Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="ZS Block Format" size="4" start="0:4" type="Block Format"/>
<field name="ZS MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="CRC Render Target" size="4" start="0:13" type="uint"/>
<field name="S Write Format" size="4" start="0:16" type="S Format"/>
<field name="S Block Format" size="4" start="0:20" type="Block Format"/>
<field name="S MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<struct name="CRC" align="64" size="16">
<field name="Render Target" size="3" start="0:13" type="uint"/>
<field name="Row Stride" size="27" start="1:0" type="uint"/>
<field name="Clear Color" size="64" start="2:0" type="hex"/>
<field name="Base" size="64" start="4:0" type="address"/>
</struct>
<field name="AFBC Reverse Issue Order" size="1" start="0:30" type="bool"/>
<struct name="ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="Block Format" size="4" start="0:4" type="Block Format"/>
<field name="MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Base" size="64" start="8:0" type="address"/>
<field name="Row Stride" size="27" start="10:0" type="uint"/>
<field name="Surface Stride hi" size="5" start="10:27" type="uint"/>
<field name="Surface Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="AFBC ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="Block Format" size="4" start="0:4" type="Block Format"/>
<field name="MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="Reverse Issue Order" size="1" start="0:30" type="bool"/>
<!-- Note: Must be set if AFBC is enabled and effective_tile_size is not 16x16 -->
<field name="ZS Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="CRC Row Stride" size="32" start="1:0" type="uint"/>
<field name="CRC Clear Color" size="64" start="2:0" type="hex"/>
<field name="CRC Base" size="64" start="4:0" type="address"/>
<field name="ZS Writeback Base" size="64" start="8:0" type="address"/>
<field name="Header" size="64" start="8:0" type="address"/>
<!-- Header clumps per row (different than Bifrost's AFBC line stride) -->
<field name="ZS Writeback Row Stride" size="32" start="10:0" type="uint"/>
<field name="ZS Writeback Surface Stride" size="32" start="11:0" type="uint"/>
<field name="ZS AFBC Body Offset" size="32" start="11:0" type="uint"/>
<field name="Header Row Stride" size="27" start="10:0" type="uint"/>
<field name="Body Offset" size="32" start="11:0" type="uint"/>
</struct>
<field name="S Writeback Base" size="64" start="12:0" type="address"/>
<field name="S Writeback Row Stride" size="32" start="14:0" type="uint"/>
<field name="S Writeback Surface Stride" size="32" start="15:0" type="uint"/>
<field name="S AFBC Body Offset" size="32" start="15:0" type="uint"/>
<struct name="S Target" align="64" size="16">
<field name="Write Format" size="4" start="0:16" type="S Format"/>
<field name="Block Format" size="4" start="0:20" type="Block Format"/>
<field name="MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Base" size="64" start="12:0" type="address"/>
<field name="Row Stride" size="27" start="14:0" type="uint"/>
<field name="Surface Stride hi" size="5" start="14:27" type="uint"/>
<field name="Surface Stride" size="32" start="15:0" type="uint"/>
</struct>
<struct name="AFBC S Target" align="64" size="16">
<field name="Write Format" size="4" start="0:16" type="S Format"/>
<field name="Block Format" size="4" start="0:20" type="Block Format"/>
<field name="MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<field name="Reverse Issue Order" size="1" start="0:30" type="bool"/>
<!-- Note: Must be set if AFBC is enabled and effective_tile_size is not 16x16 -->
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Header" size="64" start="12:0" type="address"/>
<field name="Header Row Stride" size="27" start="14:0" type="uint"/>
<field name="Body Offset" size="32" start="15:0" type="uint"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="CRC" size="512" start="0" type="CRC"/>
<field name="AFBC ZS" size="512" start="0" type="AFBC ZS Target"/>
<field name="ZS" size="512" start="0" type="ZS Target"/>
<field name="AFBC S" size="512" start="0" type="AFBC S Target"/>
<field name="S" size="512" start="0" type="S Target"/>
</struct>
<enum name="YUV Conv K6">
@@ -2306,39 +2346,6 @@
<value name="256" value="1"/>
</enum>
<struct name="Render Target YUV Overlay" size="16">
<field name="Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Plane 0 Base" size="64" start="4:0" type="address"/>
<field name="Plane 1 Base" size="64" start="6:0" type="address"/>
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="32" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="Render Target AFBC Overlay" size="16">
<field name="YUV Transform" size="1" start="2:0" type="bool"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
<field name="Reverse issue order" size="1" start="2:3" type="bool"/>
<field name="Front buffer" size="1" start="2:4" type="bool"/>
<field name="Alpha hint" size="1" start="2:5" type="bool"/>
<field name="Compression mode" size="6" start="2:10" type="AFBC Compression Mode"/>
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="32" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
</struct>
<struct name="Render Target AFRC Overlay" size="16">
<field name="Writeback Format" size="8" start="1:0" type="Color Format"/>
<field name="Block Size" size="4" start="2:4" type="AFRC Block Size"/>
<field name="Format" size="8" start="2:8" type="AFRC Format"/>
</struct>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
@@ -2346,13 +2353,10 @@
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="Render Target" align="64">
<field name="YUV" size="512" start="0:0" type="Render Target YUV Overlay"/>
<field name="AFBC" size="512" start="0:0" type="Render Target AFBC Overlay"/>
<field name="AFRC" size="512" start="0:0" type="Render Target AFRC Overlay"/>
<struct name="RGB Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
@@ -2363,10 +2367,157 @@
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="RGB" size="128" start="8:0" type="RT Buffer"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="YUV Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Plane 0 Base" size="64" start="4:0" type="address"/>
<field name="Plane 1 Base" size="64" start="6:0" type="address"/>
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="27" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="27" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFBC RGB Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Transform" size="1" start="2:0" type="bool"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
<field name="Reverse issue order" size="1" start="2:3" type="bool"/>
<field name="Front buffer" size="1" start="2:4" type="bool"/>
<field name="Alpha hint" size="1" start="2:5" type="bool"/>
<field name="Compression mode" size="6" start="2:10" type="AFBC Compression Mode"/>
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="27" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFBC YUV Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="Compat"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Transform" size="1" start="2:0" type="bool" default="false"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
<field name="Reverse issue order" size="1" start="2:3" type="bool"/>
<field name="Front buffer" size="1" start="2:4" type="bool"/>
<field name="Alpha hint" size="1" start="2:5" type="bool"/>
<field name="Compression mode" size="6" start="2:10" type="AFBC Compression Mode"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="27" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFRC RGB Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="AFRC RGB"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Writeback Format" size="8" start="1:0" type="Color Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="AFRC Block Size" size="4" start="2:4" type="AFRC Block Size"/>
<field name="AFRC Format" size="8" start="2:8" type="AFRC Format"/>
<field name="Codec args" size="8" start="3:0" type="uint"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="AFRC YUV Render Target" align="64">
<field name="Writeback Mode" size="4" start="0:0" type="Writeback Mode" default="AFRC YUV"/>
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Writeback Format" size="8" start="1:0" type="Color Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="AFRC Luma Block Size" size="4" start="2:4" type="AFRC Block Size"/>
<field name="AFRC Luma Format" size="8" start="2:8" type="AFRC Format"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="AFRC Luma codec args" size="8" start="3:0" type="uint"/>
<field name="AFRC Chroma codec args" size="8" start="3:8" type="uint"/>
<field name="AFRC Chroma Block Size" size="4" start="3:20" type="AFRC Block Size"/>
<field name="AFRC Chroma Format" size="8" start="3:24" type="AFRC Format"/>
<field name="Plane 0 Base" size="64" start="4:0" type="address"/>
<field name="Plane 1 Base" size="64" start="6:0" type="address"/>
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="27" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="27" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target" align="64">
<field name="RGB" size="512" start="0:0" type="RGB Render Target"/>
<field name="YUV" size="512" start="0:0" type="YUV Render Target"/>
<field name="AFBC RGB" size="512" start="0:0" type="AFBC RGB Render Target"/>
<field name="AFBC YUV" size="512" start="0:0" type="AFBC YUV Render Target"/>
<field name="AFRC RGB" size="512" start="0:0" type="AFRC RGB Render Target"/>
<field name="AFRC YUV" size="512" start="0:0" type="AFRC YUV Render Target"/>
</struct>
<enum name="Chunk Size">
<value name="256 KiB" value="0"/>
<value name="512 KiB" value="1"/>
src/panfrost/genxml/v5.xml
+109 -56
View File
@@ -918,33 +918,50 @@
<field name="Z Clear" size="32" start="5:0" type="float"/>
</struct>
<struct name="CRC" align="64" size="16">
<field name="Base" size="64" start="0:0" type="address"/>
<field name="Row Stride" size="32" start="2:0" type="uint"/>
</struct>
<struct name="ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="3:0" type="ZS Format"/>
<field name="Block Format" size="2" start="3:4" type="Block Format"/>
<field name="MSAA" size="2" start="3:6" default="Single" type="MSAA"/>
<field name="Big Endian" size="1" start="3:8" type="bool"/>
<field name="Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="Preload Format" size="4" start="3:28" type="ZS Preload Format"/>
<field name="Base" size="64" start="4:0" type="address"/>
<field name="Row Stride" size="32" start="6:0" type="uint"/>
<field name="Surface Stride" size="32" start="7:0" type="uint"/>
</struct>
<struct name="AFBC ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="3:0" type="ZS Format"/>
<field name="Block Format" size="2" start="3:4" type="Block Format"/>
<field name="MSAA" size="2" start="3:6" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="Header" size="64" start="4:0" type="address"/>
<field name="Chunk Size" size="12" start="7:0" type="uint"/>
<field name="Sparse" size="1" start="7:16" type="bool"/>
<field name="Body" size="64" start="8:0" type="address"/>
<field name="Body Size" size="32" start="10:0" type="uint"/>
</struct>
<struct name="S Target" align="64" size="16">
<field name="Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="Write Format" size="4" start="3:16" type="S Format"/>
<field name="Block Format" size="2" start="3:20" type="Block Format"/>
<field name="MSAA" size="2" start="3:22" default="Single" type="MSAA"/>
<field name="Base" size="64" start="8:0" type="address"/>
<field name="Row Stride" size="32" start="10:0" type="uint"/>
<field name="Surface Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="CRC Base" size="64" start="0:0" type="address"/>
<field name="CRC Row Stride" size="32" start="2:0" type="uint"/>
<field name="ZS Write Format" size="4" start="3:0" type="ZS Format"/>
<field name="ZS Block Format" size="2" start="3:4" type="Block Format"/>
<field name="ZS MSAA" size="2" start="3:6" default="Single" type="MSAA"/>
<field name="ZS Big Endian" size="1" start="3:8" type="bool"/>
<field name="ZS Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="S Write Format" size="4" start="3:16" type="S Format"/>
<field name="S Block Format" size="2" start="3:20" type="Block Format"/>
<field name="S MSAA" size="2" start="3:22" default="Single" type="MSAA"/>
<field name="ZS Preload Format" size="4" start="3:28" type="ZS Preload Format"/>
<field name="ZS Writeback Base" size="64" start="4:0" type="address"/>
<field name="ZS Writeback Row Stride" size="32" start="6:0" type="uint"/>
<field name="ZS Writeback Surface Stride" size="32" start="7:0" type="uint"/>
<field name="S Writeback Base" size="64" start="8:0" type="address"/>
<field name="S Writeback Row Stride" size="32" start="10:0" type="uint"/>
<field name="S Writeback Surface Stride" size="32" start="11:0" type="uint"/>
<field name="ZS AFBC Header" size="64" start="4:0" type="address"/>
<field name="ZS AFBC Row Stride" size="13" start="6:0" type="uint"/>
<field name="ZS AFBC Chunk Size" size="12" start="7:0" type="uint"/>
<field name="ZS AFBC Sparse" size="1" start="7:16" type="bool"/>
<field name="ZS AFBC Body" size="64" start="8:0" type="address"/>
<field name="ZS AFBC Body Size" size="32" start="10:0" type="uint"/>
<field name="ZS Preload Base" size="64" start="12:0" type="address"/>
<field name="ZS Preload Row Stride" size="32" start="14:0" type="uint"/>
<field name="ZS Preload Surface Stride" size="32" start="15:0" type="uint"/>
<field name="CRC" size="512" start="0" type="CRC"/>
<field name="ZS" size="512" start="0" type="ZS Target"/>
<field name="AFBC ZS" size="512" start="0" type="AFBC ZS Target"/>
<field name="S" size="512" start="0" type="S Target"/>
</struct>
<enum name="RT Endianness">
@@ -971,7 +988,58 @@
<value name="256" value="1"/>
</enum>
<struct name="Render Target YUV Overlay" size="16">
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="RGB Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
<field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="uint"/>
<field name="Writeback Sampling Mode" size="2" start="1:29" type="Downsampling Accumulation Mode"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="Preload Enable" size="1" start="2:0" type="bool"/>
<field name="Unload Enable" size="1" start="2:1" type="bool"/>
<field name="Preload Format" size="5" start="2:3" type="Color Format"/>
<field name="Preload Endianness" size="2" start="2:8" type="RT Endianness"/>
<field name="Preload Block Format" size="2" start="2:10" type="Block Format"/>
<field name="Preload MSAA" size="2" start="2:12" type="MSAA"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Preload buffer" size="128" start="12:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="YUV Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
<field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="uint"/>
<field name="Writeback Sampling Mode" size="2" start="1:29" type="Downsampling Accumulation Mode"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="Preload Enable" size="1" start="2:0" type="bool"/>
<field name="Unload Enable" size="1" start="2:1" type="bool"/>
<field name="Preload Format" size="5" start="2:3" type="Color Format"/>
<field name="Preload Endianness" size="2" start="2:8" type="RT Endianness"/>
<field name="Preload Block Format" size="2" start="2:10" type="Block Format"/>
<field name="Preload MSAA" size="2" start="2:12" type="MSAA"/>
<field name="Conv K5" size="8" start="2:16" type="uint"/>
<field name="Conv K6" size="1" start="2:24" type="YUV Conv K6"/>
<field name="Conv K7 Clamp" size="2" start="2:25" type="YUV Conv K7 Clamp"/>
@@ -988,28 +1056,9 @@
<field name="Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="Render Target AFBC Overlay" size="16">
<field name="Header" size="64" start="4:0" type="address"/>
<field name="Row Stride" size="13" start="6:0" type="uint"/>
<field name="Chunk Size" size="12" start="7:0" type="uint"/>
<field name="Sparse" size="1" start="7:16" type="bool"/>
<field name="YUV Transform" size="1" start="7:17" type="bool"/>
<field name="Body" size="64" start="8:0" type="address"/>
<field name="Body Size" size="32" start="10:0" type="uint"/>
</struct>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="Render Target" align="64">
<field name="YUV" size="512" start="0:0" type="Render Target YUV Overlay"/>
<field name="AFBC" size="512" start="0:0" type="Render Target AFBC Overlay"/>
<struct name="AFBC RGB Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
@@ -1021,17 +1070,21 @@
<field name="Swizzle" size="12" start="1:16" type="uint"/>
<field name="Writeback Sampling Mode" size="2" start="1:29" type="Downsampling Accumulation Mode"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="Preload Enable" size="1" start="2:0" type="bool"/>
<field name="Unload Enable" size="1" start="2:1" type="bool"/>
<field name="Preload Format" size="5" start="2:3" type="Color Format"/>
<field name="Preload Endianness" size="2" start="2:8" type="RT Endianness"/>
<field name="Preload Block Format" size="4" start="2:10" type="Block Format"/>
<field name="Preload MSAA" size="2" start="2:14" type="MSAA"/>
<field name="RGB" size="128" start="8:0" type="RT Buffer"/>
<field name="Preload buffer" size="128" start="12:0" type="RT Buffer"/>
<field name="Header" size="64" start="4:0" type="address"/>
<field name="Chunk size" size="12" start="7:0" type="uint"/>
<field name="Sparse" size="1" start="7:16" type="bool" default="false"/>
<field name="YUV Transform" size="1" start="7:17" type="bool" default="false"/>
<field name="Body" size="64" start="8:0" type="address"/>
<field name="Body Size" size="32" start="10:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target" align="64">
<field name="RGB" size="512" start="0:0" type="RGB Render Target"/>
<field name="YUV" size="512" start="0:0" type="YUV Render Target"/>
<field name="AFBC RGB" size="512" start="0:0" type="AFBC RGB Render Target"/>
</struct>
<aggregate name="Framebuffer" align="64">
<section name="Local Storage" offset="0" type="Local Storage"/>
<section name="Parameters" offset="32" type="Framebuffer Parameters"/>
src/panfrost/genxml/v6.xml
+127 -34
View File
@@ -980,26 +980,51 @@
<field name="Tiler" size="64" start="14:0" type="address"/>
</struct>
<struct name="CRC" align="64" size="16">
<field name="Base" size="64" start="0:0" type="address"/>
<field name="Row Stride" size="32" start="2:0" type="uint"/>
</struct>
<struct name="ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="3:0" type="ZS Format"/>
<field name="Block Format" size="2" start="3:4" type="Block Format"/>
<field name="MSAA" size="2" start="3:6" default="Single" type="MSAA"/>
<field name="Big Endian" size="1" start="3:8" type="bool"/>
<field name="Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="Base" size="64" start="4:0" type="address"/>
<field name="Row Stride" size="32" start="6:0" type="uint"/>
<field name="Surface Stride" size="32" start="7:0" type="uint"/>
<field name="Preload Base" size="64" start="12:0" type="address"/>
<field name="Preload Row Stride" size="32" start="14:0" type="uint"/>
<field name="Preload Surface Stride" size="32" start="15:0" type="uint"/>
</struct>
<struct name="AFBC ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="3:0" type="ZS Format"/>
<field name="Block Format" size="2" start="3:4" type="Block Format"/>
<field name="MSAA" size="2" start="3:6" default="Single" type="MSAA"/>
<field name="Big Endian" size="1" start="3:8" type="bool"/>
<field name="Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="Header" size="64" start="4:0" type="address"/>
<field name="Header Row Stride" size="13" start="6:0" type="uint"/>
<field name="Body" size="64" start="8:0" type="address"/>
</struct>
<struct name="S Target" align="64" size="16">
<field name="Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="Write Format" size="4" start="3:16" type="S Format"/>
<field name="Block Format" size="2" start="3:20" type="Block Format"/>
<field name="MSAA" size="2" start="3:22" default="Single" type="MSAA"/>
<field name="Base" size="64" start="8:0" type="address"/>
<field name="Row Stride" size="32" start="10:0" type="uint"/>
<field name="Surface Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="CRC Base" size="64" start="0:0" type="address"/>
<field name="CRC Row Stride" size="32" start="2:0" type="uint"/>
<field name="ZS Write Format" size="4" start="3:0" type="ZS Format"/>
<field name="ZS Block Format" size="2" start="3:4" type="Block Format"/>
<field name="ZS MSAA" size="2" start="3:6" default="Single" type="MSAA"/>
<field name="ZS Big Endian" size="1" start="3:8" type="bool"/>
<field name="ZS Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="S Write Format" size="4" start="3:16" type="S Format"/>
<field name="S Block Format" size="2" start="3:20" type="Block Format"/>
<field name="S MSAA" size="2" start="3:22" default="Single" type="MSAA"/>
<field name="ZS Writeback Base" size="64" start="4:0" type="address"/>
<field name="ZS Writeback Row Stride" size="32" start="6:0" type="uint"/>
<field name="ZS Writeback Surface Stride" size="32" start="7:0" type="uint"/>
<field name="S Writeback Base" size="64" start="8:0" type="address"/>
<field name="S Writeback Row Stride" size="32" start="10:0" type="uint"/>
<field name="S Writeback Surface Stride" size="32" start="11:0" type="uint"/>
<field name="ZS AFBC Header" size="64" start="4:0" type="address"/>
<field name="ZS AFBC Row Stride" size="13" start="6:0" type="uint"/>
<field name="ZS AFBC Body" size="64" start="8:0" type="address"/>
<field name="CRC" size="512" start="0" type="CRC"/>
<field name="ZS" size="512" start="0" type="ZS Target"/>
<field name="AFBC ZS" size="512" start="0" type="AFBC ZS Target"/>
<field name="S" size="512" start="0" type="S Target"/>
</struct>
<enum name="RT Endianness">
@@ -1026,8 +1051,46 @@
<value name="256" value="1"/>
</enum>
<struct name="Render Target YUV Overlay" size="16">
<field name="Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="RGB Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
<field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="YUV Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
<field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
@@ -1037,9 +1100,23 @@
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="32" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target AFBC Overlay" size="16">
<struct name="AFBC RGB Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Endianness" size="2" start="1:8" type="RT Endianness"/>
<field name="Writeback Block Format" size="2" start="1:10" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="Header" size="64" start="4:0" type="address"/>
<field name="Row Stride" size="13" start="6:0" type="uint"/>
<field name="Chunk Size" size="12" start="7:0" type="uint"/>
@@ -1053,20 +1130,12 @@
<field name="YUV Transform" size="1" start="7:17" type="bool"/>
<field name="Body" size="64" start="8:0" type="address"/>
<field name="Body Size" size="32" start="10:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="Render Target" align="64">
<field name="YUV" size="512" start="0:0" type="Render Target YUV Overlay"/>
<field name="AFBC" size="512" start="0:0" type="Render Target AFBC Overlay"/>
<struct name="AFBC YUV Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
@@ -1078,10 +1147,34 @@
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="RGB" size="128" start="8:0" type="RT Buffer"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Header" size="64" start="4:0" type="address"/>
<field name="Row Stride" size="13" start="6:0" type="uint"/>
<field name="Chunk Size" size="12" start="7:0" type="uint"/>
<field name="Split Block" size="1" start="7:18" type="bool"/>
<field name="Wide Block" size="1" start="7:19" type="bool" default="false"/>
<!-- Flag in v7 to effectively disable AFBC as a race condition workaround
when in-place rendering is used with the AFBC block size differing
from the effective tile size (XXX: does v6 need a different workaround?) -->
<field name="Reverse Issue Order" size="1" start="7:20" type="bool"/>
<field name="YUV Transform" size="1" start="7:17" type="bool" default="false"/>
<field name="Body" size="64" start="8:0" type="address"/>
<field name="Body Size" size="32" start="10:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target" align="64">
<field name="RGB" size="512" start="0:0" type="RGB Render Target"/>
<field name="YUV" size="512" start="0:0" type="YUV Render Target"/>
<field name="AFBC RGB" size="512" start="0:0" type="AFBC RGB Render Target"/>
<field name="AFBC YUV" size="512" start="0:0" type="AFBC YUV Render Target"/>
</struct>
<struct name="Tiler Heap" align="64">
<field name="Size" size="32" start="1:0" type="uint" modifier="align(4096)"/>
<field name="Base" size="64" start="2:0" type="address"/>
src/panfrost/genxml/v7.xml
+121 -35
View File
@@ -1075,27 +1075,48 @@
<field name="Tiler" size="64" start="14:0" type="address"/>
</struct>
<struct name="CRC" align="64" size="16">
<field name="Base" size="64" start="0:0" type="address"/>
<field name="Row Stride" size="32" start="2:0" type="uint"/>
<field name="Render Target" size="3" start="3:11" type="uint"/>
<field name="Clear Color" size="64" start="12:0" type="uint"/>
</struct>
<struct name="ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="3:0" type="ZS Format"/>
<field name="Block Format" size="4" start="3:4" type="Block Format"/>
<field name="MSAA" size="2" start="3:8" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="Base" size="64" start="4:0" type="address"/>
<field name="Row Stride" size="32" start="6:0" type="uint"/>
<field name="Surface Stride" size="32" start="7:0" type="uint"/>
</struct>
<struct name="AFBC ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="3:0" type="ZS Format"/>
<field name="Block Format" size="4" start="3:4" type="Block Format"/>
<field name="MSAA" size="2" start="3:8" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="Header" size="64" start="4:0" type="address"/>
<field name="Header Row Stride" size="13" start="6:0" type="uint"/>
<field name="Body" size="64" start="8:0" type="address"/>
</struct>
<struct name="S Target" align="64" size="16">
<field name="Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="Write Format" size="4" start="3:16" type="S Format"/>
<field name="Block Format" size="4" start="3:20" type="Block Format"/>
<field name="MSAA" size="2" start="3:24" default="Single" type="MSAA"/>
<field name="Base" size="64" start="8:0" type="address"/>
<field name="Row Stride" size="32" start="10:0" type="uint"/>
<field name="Surface Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="CRC Base" size="64" start="0:0" type="address"/>
<field name="CRC Row Stride" size="32" start="2:0" type="uint"/>
<field name="ZS Write Format" size="4" start="3:0" type="ZS Format"/>
<field name="ZS Block Format" size="4" start="3:4" type="Block Format"/>
<field name="ZS MSAA" size="2" start="3:8" default="Single" type="MSAA"/>
<field name="ZS Clean Pixel Write Enable" size="1" start="3:10" type="bool"/>
<field name="CRC Render Target" size="4" start="3:11" type="uint"/>
<field name="S Write Format" size="4" start="3:16" type="S Format"/>
<field name="S Block Format" size="4" start="3:20" type="Block Format"/>
<field name="S MSAA" size="2" start="3:24" default="Single" type="MSAA"/>
<field name="ZS Writeback Base" size="64" start="4:0" type="address"/>
<field name="ZS Writeback Row Stride" size="32" start="6:0" type="uint"/>
<field name="ZS Writeback Surface Stride" size="32" start="7:0" type="uint"/>
<field name="S Writeback Base" size="64" start="8:0" type="address"/>
<field name="S Writeback Row Stride" size="32" start="10:0" type="uint"/>
<field name="S Writeback Surface Stride" size="32" start="11:0" type="uint"/>
<field name="ZS AFBC Header" size="64" start="4:0" type="address"/>
<field name="ZS AFBC Row Stride" size="13" start="6:0" type="uint"/>
<field name="ZS AFBC Body" size="64" start="8:0" type="address"/>
<field name="CRC Clear Color" size="64" start="12:0" type="uint"/>
<field name="CRC" size="512" start="0" type="CRC"/>
<field name="ZS" size="512" start="0" type="ZS Target"/>
<field name="AFBC ZS" size="512" start="0" type="AFBC ZS Target"/>
<field name="S" size="512" start="0" type="S Target"/>
</struct>
<enum name="YUV Conv K6">
@@ -1115,8 +1136,44 @@
<value name="256" value="1"/>
</enum>
<struct name="Render Target YUV Overlay" size="16">
<field name="Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="RGB Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="YUV Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
@@ -1126,9 +1183,22 @@
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="32" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target AFBC Overlay" size="16">
<struct name="AFBC RGB Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="Header" size="64" start="4:0" type="address"/>
<field name="Row Stride" size="13" start="6:0" type="uint"/>
<field name="Chunk Size" size="12" start="7:0" type="uint"/>
@@ -1142,20 +1212,12 @@
<field name="YUV Transform" size="1" start="7:17" type="bool"/>
<field name="Body" size="64" start="8:0" type="address"/>
<field name="Body Size" size="32" start="10:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="Render Target" align="64">
<field name="YUV" size="512" start="0:0" type="Render Target YUV Overlay"/>
<field name="AFBC" size="512" start="0:0" type="Render Target AFBC Overlay"/>
<struct name="AFBC YUV Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
@@ -1166,10 +1228,34 @@
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="RGB" size="128" start="8:0" type="RT Buffer"/>
<field name="YUV swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Header" size="64" start="4:0" type="address"/>
<field name="Row Stride" size="13" start="6:0" type="uint"/>
<field name="Chunk Size" size="12" start="7:0" type="uint"/>
<field name="Split Block" size="1" start="7:18" type="bool"/>
<field name="Wide Block" size="1" start="7:19" type="bool"/>
<!-- Flag in v7 to effectively disable AFBC as a race condition workaround
when in-place rendering is used with the AFBC block size differing
from the effective tile size (XXX: does v6 need a different workaround?) -->
<field name="Reverse Issue Order" size="1" start="7:20" type="bool"/>
<field name="YUV Transform" size="1" start="7:17" type="bool"/>
<field name="Body" size="64" start="8:0" type="address"/>
<field name="Body Size" size="32" start="10:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target" align="64">
<field name="RGB" size="512" start="0:0" type="RGB Render Target"/>
<field name="YUV" size="512" start="0:0" type="YUV Render Target"/>
<field name="AFBC RGB" size="512" start="0:0" type="AFBC RGB Render Target"/>
<field name="AFBC YUV" size="512" start="0:0" type="AFBC YUV Render Target"/>
</struct>
<struct name="Tiler Heap" align="64">
<field name="Size" size="32" start="1:0" type="uint" modifier="align(4096)"/>
<field name="Base" size="64" start="2:0" type="address"/>
src/panfrost/genxml/v9.xml
+137 -37
View File
@@ -1097,33 +1097,70 @@
<field name="Tiler" size="64" start="14:0" type="address"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="ZS Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="ZS Block Format" size="4" start="0:4" type="Block Format"/>
<field name="ZS MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="CRC Render Target" size="4" start="0:13" type="uint"/>
<field name="S Write Format" size="4" start="0:16" type="S Format"/>
<field name="S Block Format" size="4" start="0:20" type="Block Format"/>
<field name="S MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<struct name="CRC" align="64" size="16">
<field name="Render Target" size="3" start="0:13" type="uint"/>
<field name="Row Stride" size="32" start="1:0" type="uint"/>
<field name="Clear Color" size="64" start="2:0" type="hex"/>
<field name="Base" size="64" start="4:0" type="address"/>
</struct>
<field name="AFBC Reverse Issue Order" size="1" start="0:30" type="bool"/>
<struct name="ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="Block Format" size="4" start="0:4" type="Block Format"/>
<field name="MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Base" size="64" start="8:0" type="address"/>
<field name="Row Stride" size="32" start="10:0" type="uint"/>
<field name="Surface Stride" size="32" start="11:0" type="uint"/>
</struct>
<struct name="AFBC ZS Target" align="64" size="16">
<field name="Write Format" size="4" start="0:0" type="ZS Format"/>
<field name="Block Format" size="4" start="0:4" type="Block Format"/>
<field name="MSAA" size="2" start="0:8" default="Single" type="MSAA"/>
<field name="Reverse Issue Order" size="1" start="0:30" type="bool"/>
<!-- Note: Must be set if AFBC is enabled and effective_tile_size is not 16x16 -->
<field name="ZS Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="CRC Row Stride" size="32" start="1:0" type="uint"/>
<field name="CRC Clear Color" size="64" start="2:0" type="hex"/>
<field name="CRC Base" size="64" start="4:0" type="address"/>
<field name="ZS Writeback Base" size="64" start="8:0" type="address"/>
<field name="Header" size="64" start="8:0" type="address"/>
<!-- Header clumps per row (different than Bifrost's AFBC line stride) -->
<field name="ZS Writeback Row Stride" size="32" start="10:0" type="uint"/>
<field name="ZS Writeback Surface Stride" size="32" start="11:0" type="uint"/>
<field name="ZS AFBC Body Offset" size="32" start="11:0" type="uint"/>
<field name="Header Row Stride" size="32" start="10:0" type="uint"/>
<field name="Body Offset" size="32" start="11:0" type="uint"/>
</struct>
<field name="S Writeback Base" size="64" start="12:0" type="address"/>
<field name="S Writeback Row Stride" size="32" start="14:0" type="uint"/>
<field name="S Writeback Surface Stride" size="32" start="15:0" type="uint"/>
<field name="S AFBC Body Offset" size="32" start="15:0" type="uint"/>
<struct name="S Target" align="64" size="16">
<field name="Write Format" size="4" start="0:16" type="S Format"/>
<field name="Block Format" size="4" start="0:20" type="Block Format"/>
<field name="MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Base" size="64" start="12:0" type="address"/>
<field name="Row Stride" size="32" start="14:0" type="uint"/>
<field name="Surface Stride" size="32" start="15:0" type="uint"/>
</struct>
<struct name="AFBC S Target" align="64" size="16">
<field name="Write Format" size="4" start="0:16" type="S Format"/>
<field name="Block Format" size="4" start="0:20" type="Block Format"/>
<field name="MSAA" size="2" start="0:24" default="Single" type="MSAA"/>
<field name="Reverse Issue Order" size="1" start="0:30" type="bool"/>
<!-- Note: Must be set if AFBC is enabled and effective_tile_size is not 16x16 -->
<field name="Clean Pixel Write Enable" size="1" start="0:31" type="bool"/>
<field name="Header" size="64" start="12:0" type="address"/>
<field name="Header Row Stride" size="32" start="14:0" type="uint"/>
<field name="Body Offset" size="32" start="15:0" type="uint"/>
</struct>
<struct name="ZS CRC Extension" align="64" size="16">
<field name="CRC" size="512" start="0" type="CRC"/>
<field name="AFBC ZS" size="512" start="0" type="AFBC ZS Target"/>
<field name="ZS" size="512" start="0" type="ZS Target"/>
<field name="AFBC S" size="512" start="0" type="AFBC S Target"/>
<field name="S" size="512" start="0" type="S Target"/>
</struct>
<enum name="YUV Conv K6">
@@ -1143,8 +1180,44 @@
<value name="256" value="1"/>
</enum>
<struct name="Render Target YUV Overlay" size="16">
<field name="Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="RGB Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="Writeback buffer" size="128" start="8:0" type="RT Buffer"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="YUV Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
@@ -1154,9 +1227,22 @@
<field name="Plane 2 Base" size="64" start="8:0" type="address"/>
<field name="Plane 0 Stride" size="32" start="10:0" type="uint"/>
<field name="Plane 1 2 Stride" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target AFBC Overlay" size="16">
<struct name="AFBC RGB Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="false"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
<field name="Writeback Format" size="5" start="1:3" type="Color Format"/>
<field name="Writeback Block Format" size="4" start="1:8" type="Block Format"/>
<field name="Writeback MSAA" size="2" start="1:12" type="MSAA"/>
<field name="sRGB" size="1" start="1:14" type="bool"/>
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="YUV Transform" size="1" start="2:0" type="bool"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
@@ -1168,20 +1254,12 @@
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="32" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="RT Clear">
<field name="Color 0" size="32" start="0:0" type="uint"/>
<field name="Color 1" size="32" start="1:0" type="uint"/>
<field name="Color 2" size="32" start="2:0" type="uint"/>
<field name="Color 3" size="32" start="3:0" type="uint"/>
</struct>
<struct name="Render Target" align="64">
<field name="YUV" size="512" start="0:0" type="Render Target YUV Overlay"/>
<field name="AFBC" size="512" start="0:0" type="Render Target AFBC Overlay"/>
<struct name="AFBC YUV Render Target" align="64">
<field name="Internal Buffer Offset" size="12" start="0:4" type="uint" modifier="shr(4)"/>
<field name="YUV Enable" size="1" start="0:24" type="bool"/>
<field name="YUV Enable" size="1" start="0:24" type="bool" default="true"/>
<field name="Dithered Clear" size="1" start="0:25" type="bool"/>
<field name="Internal Format" size="6" start="0:26" type="Color Buffer Internal Format"/>
<field name="Write Enable" size="1" start="1:0" type="bool"/>
@@ -1192,10 +1270,32 @@
<field name="Dithering Enable" size="1" start="1:15" type="bool"/>
<field name="Swizzle" size="12" start="1:16" type="Component Swizzle"/>
<field name="Clean Pixel Write Enable" size="1" start="1:31" type="bool"/>
<field name="RGB" size="128" start="8:0" type="RT Buffer"/>
<field name="YUV Transform" size="1" start="2:0" type="bool" defaut="false"/>
<field name="Split block" size="1" start="2:1" type="bool"/>
<field name="Wide block" size="1" start="2:2" type="bool"/>
<field name="Reverse issue order" size="1" start="2:3" type="bool"/>
<field name="Front buffer" size="1" start="2:4" type="bool"/>
<field name="Alpha hint" size="1" start="2:5" type="bool"/>
<field name="Compression mode" size="6" start="2:10" type="AFBC Compression Mode"/>
<field name="YUV Swizzle" size="3" start="2:16" type="YUV Swizzle"/>
<field name="Full Range" size="1" start="2:20" type="bool"/>
<field name="Conversion Mode" size="4" start="2:21" type="YUV Conversion Mode"/>
<field name="Cr Siting" size="3" start="2:25" type="YUV Cr Siting"/>
<field name="Unsigned Cr Range" size="1" start="2:28" type="bool"/>
<field name="Header" size="64" start="8:0" type="address"/>
<field name="Row stride" size="32" start="10:0" type="uint"/>
<field name="Body offset" size="32" start="11:0" type="uint"/>
<field name="Clear" size="128" start="12:0" type="RT Clear"/>
</struct>
<struct name="Render Target" align="64">
<field name="RGB" size="512" start="0:0" type="RGB Render Target"/>
<field name="YUV" size="512" start="0:0" type="YUV Render Target"/>
<field name="AFBC RGB" size="512" start="0:0" type="AFBC RGB Render Target"/>
<field name="AFBC YUV" size="512" start="0:0" type="AFBC YUV Render Target"/>
</struct>
<enum name="Chunk Size">
<value name="256 KiB" value="0"/>
<value name="512 KiB" value="1"/>
src/panfrost/lib/pan_desc.c
+214 -168
View File
@@ -234,15 +234,18 @@ GENX(pan_emit_linear_s_attachment)(const struct pan_fb_info *fb,
unsigned layer_or_z_slice, void *payload)
{
const struct pan_image_view *s = fb->zs.view.s;
uint64_t base, row_stride, surf_stride;
pan_cast_and_pack(payload, ZS_CRC_EXTENSION, cfg) {
cfg.s_msaa = mali_sampling_mode(s);
cfg.s_write_format = translate_s_format(s->format);
cfg.s_block_format = MALI_BLOCK_FORMAT_LINEAR;
get_tiled_or_linear_att_mem_props(
pan_image_view_get_s_plane(s), s->first_level, layer_or_z_slice,
&cfg.s_writeback_base, &cfg.s_writeback_row_stride,
&cfg.s_writeback_surface_stride);
get_tiled_or_linear_att_mem_props(pan_image_view_get_s_plane(s),
s->first_level, layer_or_z_slice, &base,
&row_stride, &surf_stride);
pan_cast_and_pack(payload, S_TARGET, cfg) {
cfg.msaa = mali_sampling_mode(s);
cfg.write_format = translate_s_format(s->format);
cfg.block_format = MALI_BLOCK_FORMAT_LINEAR;
cfg.base = base;
cfg.row_stride = row_stride;
cfg.surface_stride = surf_stride;
}
}
@@ -255,15 +258,17 @@ GENX(pan_emit_afbc_s_attachment)(const struct pan_fb_info *fb,
#if PAN_ARCH >= 9
const struct pan_image_view *s = fb->zs.view.s;
const struct pan_image_plane_ref pref = pan_image_view_get_s_plane(s);
uint64_t header, body_offset, hdr_row_stride;
pan_cast_and_pack(payload, ZS_CRC_EXTENSION, cfg) {
cfg.s_msaa = mali_sampling_mode(s);
cfg.s_write_format = translate_zs_format(s->format);
cfg.s_block_format = get_afbc_block_format(pref.image->props.modifier);
get_afbc_att_mem_props(pref, s->first_level, layer_or_z_slice,
&cfg.s_writeback_base, &cfg.s_afbc_body_offset,
&cfg.s_writeback_row_stride);
get_afbc_att_mem_props(pref, s->first_level, layer_or_z_slice, &header,
&body_offset, &hdr_row_stride);
pan_cast_and_pack(payload, AFBC_S_TARGET, cfg) {
cfg.msaa = mali_sampling_mode(s);
cfg.write_format = translate_zs_format(s->format);
cfg.block_format = get_afbc_block_format(pref.image->props.modifier);
cfg.header = header;
cfg.body_offset = body_offset;
cfg.header_row_stride = hdr_row_stride;
}
#endif
}
@@ -273,15 +278,18 @@ GENX(pan_emit_u_tiled_s_attachment)(const struct pan_fb_info *fb,
unsigned layer_or_z_slice, void *payload)
{
const struct pan_image_view *s = fb->zs.view.s;
uint64_t base, row_stride, surf_stride;
pan_cast_and_pack(payload, ZS_CRC_EXTENSION, cfg) {
cfg.s_msaa = mali_sampling_mode(s);
cfg.s_write_format = translate_s_format(s->format);
cfg.s_block_format = MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
get_tiled_or_linear_att_mem_props(
pan_image_view_get_s_plane(s), s->first_level, layer_or_z_slice,
&cfg.s_writeback_base, &cfg.s_writeback_row_stride,
&cfg.s_writeback_surface_stride);
get_tiled_or_linear_att_mem_props(pan_image_view_get_s_plane(s),
s->first_level, layer_or_z_slice, &base,
&row_stride, &surf_stride);
pan_cast_and_pack(payload, S_TARGET, cfg) {
cfg.msaa = mali_sampling_mode(s);
cfg.write_format = translate_s_format(s->format);
cfg.block_format = MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
cfg.base = base;
cfg.row_stride = row_stride;
cfg.surface_stride = surf_stride;
}
}
@@ -290,18 +298,18 @@ GENX(pan_emit_linear_zs_attachment)(const struct pan_fb_info *fb,
unsigned layer_or_z_slice, void *payload)
{
const struct pan_image_view *zs = fb->zs.view.zs;
uint64_t base, row_stride, surf_stride;
pan_cast_and_pack(payload, ZS_CRC_EXTENSION, cfg) {
cfg.zs_msaa = mali_sampling_mode(zs);
cfg.zs_write_format = translate_zs_format(zs->format);
cfg.zs_block_format = MALI_BLOCK_FORMAT_LINEAR;
get_tiled_or_linear_att_mem_props(
pan_image_view_get_zs_plane(zs), zs->first_level, layer_or_z_slice,
&cfg.zs_writeback_base, &cfg.zs_writeback_row_stride,
&cfg.zs_writeback_surface_stride);
if (cfg.zs_write_format == MALI_ZS_FORMAT_D24S8)
cfg.s_writeback_base = cfg.zs_writeback_base;
get_tiled_or_linear_att_mem_props(pan_image_view_get_zs_plane(zs),
zs->first_level, layer_or_z_slice, &base,
&row_stride, &surf_stride);
pan_cast_and_pack(payload, ZS_TARGET, cfg) {
cfg.msaa = mali_sampling_mode(zs);
cfg.write_format = translate_zs_format(zs->format);
cfg.block_format = MALI_BLOCK_FORMAT_LINEAR;
cfg.base = base;
cfg.row_stride = row_stride;
cfg.surface_stride = surf_stride;
}
}
@@ -310,18 +318,18 @@ GENX(pan_emit_u_tiled_zs_attachment)(const struct pan_fb_info *fb,
unsigned layer_or_z_slice, void *payload)
{
const struct pan_image_view *zs = fb->zs.view.zs;
uint64_t base, row_stride, surf_stride;
pan_cast_and_pack(payload, ZS_CRC_EXTENSION, cfg) {
cfg.zs_msaa = mali_sampling_mode(zs);
cfg.zs_write_format = translate_zs_format(zs->format);
cfg.zs_block_format = MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
get_tiled_or_linear_att_mem_props(
pan_image_view_get_zs_plane(zs), zs->first_level, layer_or_z_slice,
&cfg.zs_writeback_base, &cfg.zs_writeback_row_stride,
&cfg.zs_writeback_surface_stride);
if (cfg.zs_write_format == MALI_ZS_FORMAT_D24S8)
cfg.s_writeback_base = cfg.zs_writeback_base;
get_tiled_or_linear_att_mem_props(pan_image_view_get_zs_plane(zs),
zs->first_level, layer_or_z_slice, &base,
&row_stride, &surf_stride);
pan_cast_and_pack(payload, ZS_TARGET, cfg) {
cfg.msaa = mali_sampling_mode(zs);
cfg.write_format = translate_zs_format(zs->format);
cfg.block_format = MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
cfg.base = base;
cfg.row_stride = row_stride;
cfg.surface_stride = surf_stride;
}
}
@@ -331,30 +339,31 @@ GENX(pan_emit_afbc_zs_attachment)(const struct pan_fb_info *fb,
{
const struct pan_image_view *zs = fb->zs.view.zs;
const struct pan_image_plane_ref pref = pan_image_view_get_zs_plane(zs);
uint64_t header, body_offset, hdr_row_stride;
pan_cast_and_pack(payload, ZS_CRC_EXTENSION, cfg) {
cfg.zs_msaa = mali_sampling_mode(zs);
cfg.zs_write_format = translate_zs_format(zs->format);
cfg.zs_block_format = get_afbc_block_format(pref.image->props.modifier);
get_afbc_att_mem_props(pref, zs->first_level, layer_or_z_slice, &header,
&body_offset, &hdr_row_stride);
pan_cast_and_pack(payload, AFBC_ZS_TARGET, cfg) {
cfg.msaa = mali_sampling_mode(zs);
cfg.write_format = translate_zs_format(zs->format);
cfg.block_format = get_afbc_block_format(pref.image->props.modifier);
#if PAN_ARCH >= 9
get_afbc_att_mem_props(pref, zs->first_level, layer_or_z_slice,
&cfg.zs_writeback_base, &cfg.zs_afbc_body_offset,
&cfg.zs_writeback_row_stride);
cfg.header = header;
cfg.body_offset = body_offset;
cfg.header_row_stride = hdr_row_stride;
#else
uint64_t body_offset, row_stride;
get_afbc_att_mem_props(pref, zs->first_level, layer_or_z_slice,
&cfg.zs_afbc_header, &body_offset, &row_stride);
cfg.zs_afbc_body = cfg.zs_afbc_header + body_offset;
cfg.header = header;
cfg.body = header + body_offset;
#if PAN_ARCH >= 6
cfg.zs_afbc_row_stride =
pan_afbc_stride_blocks(pref.image->props.modifier, row_stride);
cfg.header_row_stride =
pan_afbc_stride_blocks(pref.image->props.modifier, hdr_row_stride);
#else
cfg.zs_afbc_body_size = 0x1000;
cfg.zs_afbc_chunk_size = 9;
cfg.zs_afbc_sparse = true;
cfg.body_size = 0x1000;
cfg.chunk_size = 9;
cfg.sparse = true;
#endif
#endif
}
@@ -362,7 +371,7 @@ GENX(pan_emit_afbc_zs_attachment)(const struct pan_fb_info *fb,
static void
pan_prepare_crc(const struct pan_fb_info *fb, int rt_crc,
struct MALI_ZS_CRC_EXTENSION *ext)
struct MALI_CRC *crc)
{
if (rt_crc < 0)
return;
@@ -376,16 +385,16 @@ pan_prepare_crc(const struct pan_fb_info *fb, int rt_crc,
const struct pan_image_slice_layout *slice =
&plane->layout.slices[rt->first_level];
ext->crc_base = plane->base + slice->crc.offset_B;
ext->crc_row_stride = slice->crc.stride_B;
crc->base = plane->base + slice->crc.offset_B;
crc->row_stride = slice->crc.stride_B;
#if PAN_ARCH >= 7
ext->crc_render_target = rt_crc;
crc->render_target = rt_crc;
if (fb->rts[rt_crc].clear) {
uint32_t clear_val = fb->rts[rt_crc].clear_value[0];
ext->crc_clear_color = clear_val | 0xc000000000000000 |
(((uint64_t)clear_val & 0xffff) << 32);
crc->clear_color = clear_val | 0xc000000000000000 |
(((uint64_t)clear_val & 0xffff) << 32);
}
#endif
}
@@ -397,8 +406,8 @@ pan_emit_zs_crc_ext(const struct pan_fb_info *fb, unsigned layer_idx,
struct mali_zs_crc_extension_packed desc;
pan_pack(&desc, ZS_CRC_EXTENSION, cfg) {
pan_prepare_crc(fb, rt_crc, &cfg);
cfg.zs_clean_pixel_write_enable = fb->zs.clear.z || fb->zs.clear.s;
pan_prepare_crc(fb, rt_crc, &cfg.crc);
cfg.zs.clean_pixel_write_enable = fb->zs.clear.z || fb->zs.clear.s;
}
if (fb->zs.view.zs) {
@@ -572,17 +581,14 @@ pan_mfbd_raw_format(unsigned bits)
/* clang-format on */
}
static unsigned
pan_rt_init_format(const struct pan_image_view *rt,
struct MALI_RENDER_TARGET *cfg)
static void
get_rt_formats(enum pipe_format pfmt, uint32_t *writeback, uint32_t *internal,
uint32_t *pswizzle)
{
/* Explode details on the format */
const struct util_format_description *desc =
util_format_description(rt->format);
const struct util_format_description *desc = util_format_description(pfmt);
/* The swizzle for rendering is inverted from texturing */
unsigned char swizzle[4] = {
PIPE_SWIZZLE_X,
PIPE_SWIZZLE_Y,
@@ -590,18 +596,12 @@ pan_rt_init_format(const struct pan_image_view *rt,
PIPE_SWIZZLE_W,
};
/* Fill in accordingly, defaulting to 8-bit UNORM */
const struct pan_blendable_format *bfmt =
GENX(pan_blendable_format_from_pipe_format)(pfmt);
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
cfg->srgb = true;
struct pan_blendable_format fmt =
*GENX(pan_blendable_format_from_pipe_format)(rt->format);
enum mali_color_format writeback_format;
if (fmt.internal) {
cfg->internal_format = fmt.internal;
writeback_format = fmt.writeback;
if (bfmt->internal) {
*internal = bfmt->internal;
*writeback = bfmt->writeback;
pan_invert_swizzle(desc->swizzle, swizzle);
} else {
/* Construct RAW internal/writeback, where internal is
@@ -613,95 +613,111 @@ pan_rt_init_format(const struct pan_image_view *rt,
unsigned offset = util_logbase2_ceil(bits) - 3;
assert(offset <= 4);
cfg->internal_format = MALI_COLOR_BUFFER_INTERNAL_FORMAT_RAW8 + offset;
writeback_format = pan_mfbd_raw_format(bits);
*internal = MALI_COLOR_BUFFER_INTERNAL_FORMAT_RAW8 + offset;
*writeback = pan_mfbd_raw_format(bits);
}
cfg->swizzle = pan_translate_swizzle_4(swizzle);
return writeback_format;
*pswizzle = pan_translate_swizzle_4(swizzle);
}
/* forward declaration */
static bool pan_force_clean_write_on(const struct pan_image *img, unsigned tile_size);
static void
pan_prepare_rt_common(const struct pan_fb_info *fb, unsigned rt_idx,
unsigned cbuf_offset, struct MALI_RENDER_TARGET *cfg)
static struct MALI_RT_CLEAR
rt_clear(const struct pan_fb_color_attachment *rt)
{
cfg->clean_pixel_write_enable = fb->rts[rt_idx].clear;
cfg->internal_buffer_offset = cbuf_offset;
if (fb->rts[rt_idx].clear) {
cfg->clear.color_0 = fb->rts[rt_idx].clear_value[0];
cfg->clear.color_1 = fb->rts[rt_idx].clear_value[1];
cfg->clear.color_2 = fb->rts[rt_idx].clear_value[2];
cfg->clear.color_3 = fb->rts[rt_idx].clear_value[3];
}
cfg->dithering_enable = true;
if (!rt->clear)
return (struct MALI_RT_CLEAR){0};
if (fb->rts[rt_idx].view) {
cfg->writeback_msaa = mali_sampling_mode(fb->rts[rt_idx].view);
return (struct MALI_RT_CLEAR){
.color_0 = rt->clear_value[0],
.color_1 = rt->clear_value[1],
.color_2 = rt->clear_value[2],
.color_3 = rt->clear_value[3],
};
}
static bool
rt_clean_pixel_write(const struct pan_fb_color_attachment *rt,
unsigned tile_size)
{
if (rt->clear)
return true;
#if PAN_ARCH >= 6
const struct pan_image_plane_ref pref =
pan_image_view_get_color_plane(fb->rts[rt_idx].view);
const struct pan_image_plane_ref pref =
pan_image_view_get_color_plane(rt->view);
cfg->clean_pixel_write_enable |=
pan_force_clean_write_on(pref.image, fb->tile_size);
if (pan_force_clean_write_on(pref.image, tile_size))
return true;
#endif
}
return false;
}
#define rt_common_cfg(rt__, cbuf_offset__, tile_size__, cfg__) \
do { \
assert((rt__)->view != NULL); \
(cfg__).clean_pixel_write_enable = \
rt_clean_pixel_write(rt__, tile_size__); \
(cfg__).internal_buffer_offset = cbuf_offset__; \
(cfg__).clear = rt_clear(rt__); \
(cfg__).dithering_enable = true; \
(cfg__).writeback_msaa = mali_sampling_mode((rt__)->view); \
} while (0)
void
GENX(pan_emit_afbc_color_attachment)(const struct pan_fb_info *fb,
unsigned rt_idx,
unsigned layer_or_z_slice,
unsigned cbuf_offset, void *payload)
{
const struct pan_image_view *iview = fb->rts[rt_idx].view;
const unsigned mip_level = iview->first_level;
const struct pan_fb_color_attachment *rt = &fb->rts[rt_idx];
const struct pan_image_view *iview = rt->view;
const struct pan_image_plane_ref pref = pan_image_view_get_color_plane(iview);
const struct pan_image *image = pref.image;
uint64_t header, body_offset, hdr_row_stride;
pan_cast_and_pack(payload, RENDER_TARGET, cfg) {
pan_prepare_rt_common(fb, rt_idx, cbuf_offset, &cfg);
get_afbc_att_mem_props(pref, iview->first_level, layer_or_z_slice, &header,
&body_offset, &hdr_row_stride);
/* TODO: YUV RT. */
assert(!pan_format_is_yuv(iview->format));
pan_cast_and_pack(payload, AFBC_RGB_RENDER_TARGET, cfg) {
rt_common_cfg(rt, cbuf_offset, fb->tile_size, cfg);
cfg.write_enable = true;
cfg.writeback_format = pan_rt_init_format(iview, &cfg);
get_rt_formats(iview->format, &cfg.writeback_format, &cfg.internal_format,
&cfg.swizzle);
cfg.srgb = util_format_is_srgb(iview->format);
cfg.writeback_block_format = get_afbc_block_format(image->props.modifier);
cfg.afbc.yuv_transform = image->props.modifier & AFBC_FORMAT_MOD_YTR;
cfg.yuv_transform = image->props.modifier & AFBC_FORMAT_MOD_YTR;
#if PAN_ARCH >= 6
cfg.afbc.wide_block = pan_afbc_is_wide(image->props.modifier);
cfg.afbc.split_block = (image->props.modifier & AFBC_FORMAT_MOD_SPLIT);
cfg.wide_block = pan_afbc_is_wide(image->props.modifier);
cfg.split_block = (image->props.modifier & AFBC_FORMAT_MOD_SPLIT);
#endif
#if PAN_ARCH >= 9
get_afbc_att_mem_props(pref, mip_level, layer_or_z_slice,
&cfg.afbc.header, &cfg.afbc.body_offset,
&cfg.afbc.row_stride);
cfg.afbc.compression_mode = pan_afbc_compression_mode(iview->format, 0);
cfg.header = header;
cfg.body_offset = body_offset;
cfg.row_stride = hdr_row_stride;
cfg.compression_mode = pan_afbc_compression_mode(iview->format, 0);
#else
uint64_t body_offset, row_stride;
get_afbc_att_mem_props(pref, mip_level, layer_or_z_slice,
&cfg.afbc.header, &body_offset,
&row_stride);
cfg.afbc.body = cfg.afbc.header + body_offset;
cfg.header = header;
cfg.body = header + body_offset;
#if PAN_ARCH >= 6
cfg.afbc.row_stride =
pan_afbc_stride_blocks(image->props.modifier, row_stride);
cfg.row_stride =
pan_afbc_stride_blocks(image->props.modifier, hdr_row_stride);
#else
const struct pan_image_plane *plane = image->planes[pref.plane_idx];
const struct pan_image_slice_layout *slayout =
&plane->layout.slices[mip_level];
&plane->layout.slices[iview->first_level];
cfg.afbc.body_size =
slayout->afbc.surface_stride_B -
pan_afbc_body_offset(PAN_ARCH, image->props.modifier,
slayout->afbc.header.surface_size_B);
cfg.afbc.chunk_size = 9;
cfg.afbc.sparse = true;
cfg.body_size = slayout->afbc.surface_stride_B -
pan_afbc_body_offset(PAN_ARCH, image->props.modifier,
slayout->afbc.header.surface_size_B);
cfg.chunk_size = 9;
cfg.sparse = true;
#endif
#endif
}
@@ -713,17 +729,26 @@ GENX(pan_emit_u_tiled_color_attachment)(const struct pan_fb_info *fb,
unsigned layer_or_z_slice,
unsigned cbuf_offset, void *payload)
{
const struct pan_image_view *iview = fb->rts[rt_idx].view;
const struct pan_fb_color_attachment *rt = &fb->rts[rt_idx];
const struct pan_image_view *iview = rt->view;
uint64_t base, row_stride, surf_stride;
pan_cast_and_pack(payload, RENDER_TARGET, cfg) {
pan_prepare_rt_common(fb, rt_idx, cbuf_offset, &cfg);
get_tiled_or_linear_att_mem_props(pan_image_view_get_color_plane(iview),
iview->first_level, layer_or_z_slice,
&base, &row_stride, &surf_stride);
/* TODO: YUV RT. */
assert(!pan_format_is_yuv(iview->format));
pan_cast_and_pack(payload, RGB_RENDER_TARGET, cfg) {
rt_common_cfg(rt, cbuf_offset, fb->tile_size, cfg);
cfg.write_enable = true;
cfg.writeback_block_format = MALI_BLOCK_FORMAT_TILED_U_INTERLEAVED;
cfg.writeback_format = pan_rt_init_format(iview, &cfg);
get_tiled_or_linear_att_mem_props(pan_image_view_get_color_plane(iview),
iview->first_level, layer_or_z_slice,
&cfg.rgb.base, &cfg.rgb.row_stride,
&cfg.rgb.surface_stride);
get_rt_formats(iview->format, &cfg.writeback_format, &cfg.internal_format,
&cfg.swizzle);
cfg.srgb = util_format_is_srgb(iview->format);
cfg.writeback_buffer.base = base;
cfg.writeback_buffer.row_stride = row_stride;
cfg.writeback_buffer.surface_stride = surf_stride;
}
}
@@ -733,17 +758,26 @@ GENX(pan_emit_linear_color_attachment)(const struct pan_fb_info *fb,
unsigned layer_or_z_slice,
unsigned cbuf_offset, void *payload)
{
const struct pan_image_view *iview = fb->rts[rt_idx].view;
const struct pan_fb_color_attachment *rt = &fb->rts[rt_idx];
const struct pan_image_view *iview = rt->view;
uint64_t base, row_stride, surf_stride;
pan_cast_and_pack(payload, RENDER_TARGET, cfg) {
pan_prepare_rt_common(fb, rt_idx, cbuf_offset, &cfg);
get_tiled_or_linear_att_mem_props(pan_image_view_get_color_plane(iview),
iview->first_level, layer_or_z_slice,
&base, &row_stride, &surf_stride);
/* TODO: YUV RT. */
assert(!pan_format_is_yuv(iview->format));
pan_cast_and_pack(payload, RGB_RENDER_TARGET, cfg) {
rt_common_cfg(rt, cbuf_offset, fb->tile_size, cfg);
cfg.write_enable = true;
cfg.writeback_block_format = MALI_BLOCK_FORMAT_LINEAR;
cfg.writeback_format = pan_rt_init_format(iview, &cfg);
get_tiled_or_linear_att_mem_props(pan_image_view_get_color_plane(iview),
iview->first_level, layer_or_z_slice,
&cfg.rgb.base, &cfg.rgb.row_stride,
&cfg.rgb.surface_stride);
get_rt_formats(iview->format, &cfg.writeback_format, &cfg.internal_format,
&cfg.swizzle);
cfg.srgb = util_format_is_srgb(iview->format);
cfg.writeback_buffer.base = base;
cfg.writeback_buffer.row_stride = row_stride;
cfg.writeback_buffer.surface_stride = surf_stride;
}
}
@@ -753,21 +787,30 @@ GENX(pan_emit_afrc_color_attachment)(const struct pan_fb_info *fb,
unsigned rt_idx, unsigned layer_or_z_slice,
unsigned cbuf_offset, void *payload)
{
const struct pan_image_view *iview = fb->rts[rt_idx].view;
const struct pan_fb_color_attachment *rt = &fb->rts[rt_idx];
const struct pan_image_view *iview = rt->view;
const struct pan_image_plane_ref pref = pan_image_view_get_color_plane(iview);
const struct pan_image *image = pref.image;
struct pan_afrc_format_info finfo =
pan_afrc_get_format_info(image->props.format);
uint64_t base, row_stride, surf_stride;
pan_cast_and_pack(payload, RENDER_TARGET, cfg) {
pan_prepare_rt_common(fb, rt_idx, cbuf_offset, &cfg);
get_tiled_or_linear_att_mem_props(pan_image_view_get_s_plane(iview),
iview->first_level, layer_or_z_slice,
&base, &row_stride, &surf_stride);
/* TODO: YUV RT. */
assert(!pan_format_is_yuv(iview->format));
pan_cast_and_pack(payload, AFRC_RGB_RENDER_TARGET, cfg) {
rt_common_cfg(rt, cbuf_offset, fb->tile_size, cfg);
cfg.writeback_mode = MALI_WRITEBACK_MODE_AFRC_RGB;
cfg.afrc.block_size = pan_afrc_block_size(image->props.modifier, 0);
cfg.afrc.format = pan_afrc_format(finfo, image->props.modifier, 0);
cfg.afrc.writeback_format = pan_rt_init_format(iview, &cfg);
get_tiled_or_linear_att_mem_props(
pref, iview->first_level, layer_or_z_slice, &cfg.rgb.base,
&cfg.rgb.row_stride, &cfg.rgb.surface_stride);
cfg.afrc_block_size = pan_afrc_block_size(image->props.modifier, 0);
cfg.afrc_format = pan_afrc_format(finfo, image->props.modifier, 0);
get_rt_formats(iview->format, &cfg.writeback_format, &cfg.internal_format,
&cfg.swizzle);
cfg.writeback_buffer.base = base;
cfg.writeback_buffer.row_stride = row_stride;
cfg.writeback_buffer.surface_stride = surf_stride;
}
}
#endif
@@ -856,8 +899,11 @@ pan_emit_rt(const struct pan_fb_info *fb, unsigned layer_idx, unsigned idx,
const struct pan_image_view *rt = fb->rts[idx].view;
if (!rt || fb->rts[idx].discard) {
pan_pack(out, RENDER_TARGET, cfg) {
pan_prepare_rt_common(fb, idx, cbuf_offset, &cfg);
pan_cast_and_pack(out, RGB_RENDER_TARGET, cfg) {
cfg.clean_pixel_write_enable = fb->rts[idx].clear;
cfg.internal_buffer_offset = cbuf_offset;
cfg.clear = rt_clear(&fb->rts[idx]);
cfg.dithering_enable = true;
cfg.internal_format = MALI_COLOR_BUFFER_INTERNAL_FORMAT_R8G8B8A8;
cfg.internal_buffer_offset = cbuf_offset;
#if PAN_ARCH >= 7