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intel/brw: support for dumping shader line numbers

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Add support for dumping shader asm containing instruction line numbers
matching offsets within instruction state pool buffer. Offsets
should match values collected from eu stall sampling. This is
required for match eu stall data with individual shader instructions.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30142>
This commit is contained in:
Felix DeGrood
2024-08-08 19:05:09 +00:00
committed by Marge Bot
parent 1dc90e3f8b
commit 7a3de9e877
8 changed files with 37 additions and 13 deletions
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2
src/intel/decoder/intel_batch_decoder_brw.c
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@@ -20,7 +20,7 @@ ctx_disassemble_program_brw(struct intel_batch_decode_ctx *ctx,
return;
fprintf(ctx->fp, "\nReferenced %s:\n", name);
brw_disassemble_with_errors(ctx->brw, bo.map, 0, ctx->fp);
brw_disassemble_with_errors(ctx->brw, bo.map, 0, NULL, ctx->fp);
if (ctx->shader_binary) {
int size = brw_disassemble_find_end(ctx->brw, bo.map, 0);