diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 154553e385d..ab712f1441b 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -2855,7 +2855,13 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
             bld.vop3(aco_opcode::v_med3_i16, bld.def(v2b), Operand::c16(-1), src, Operand::c16(1u));
          bld.vop1(aco_opcode::v_cvt_f16_i16, Definition(dst), src);
       } else if (dst.regClass() == v1) {
-         src = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand::zero(), src);
+         if (ctx->block->fp_mode.denorm32 == fp_denorm_flush) {
+            /* If denormals are flushed, then v_mul_legacy_f32(2.0, src) can become omod. */
+            src =
+               bld.vop2(aco_opcode::v_mul_legacy_f32, bld.def(v1), Operand::c32(0x40000000), src);
+         } else {
+            src = bld.vop2(aco_opcode::v_add_f32, bld.def(v1), Operand::zero(), src);
+         }
          src =
             bld.vop3(aco_opcode::v_med3_i32, bld.def(v1), Operand::c32(-1), src, Operand::c32(1u));
          bld.vop1(aco_opcode::v_cvt_f32_i32, Definition(dst), src);