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intel/compiler: Add gather4_i/l/[_c]/b sampler message

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v2: (Ian)
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Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27447>
This commit is contained in:
Sagar Ghuge
2023-02-16 20:30:30 -08:00
committed by Marge Bot
parent 3c7f1feebf
commit 79af0ac29a
11 changed files with 136 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_fs.cpp
+18
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@@ -274,6 +274,9 @@ fs_inst::is_control_source(unsigned arg) const
case SHADER_OPCODE_LOD:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_TG4_BIAS:
case SHADER_OPCODE_TG4_EXPLICIT_LOD:
case SHADER_OPCODE_TG4_IMPLICIT_LOD:
case SHADER_OPCODE_SAMPLEINFO:
return arg == 1 || arg == 2;
@@ -315,6 +318,9 @@ fs_inst::is_payload(unsigned arg) const
case SHADER_OPCODE_LOD:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_TG4_BIAS:
case SHADER_OPCODE_TG4_EXPLICIT_LOD:
case SHADER_OPCODE_TG4_IMPLICIT_LOD:
case SHADER_OPCODE_SAMPLEINFO:
return arg == 0;
@@ -719,6 +725,9 @@ fs_inst::components_read(unsigned i) const
case SHADER_OPCODE_LOD_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
case SHADER_OPCODE_TG4_BIAS_LOGICAL:
case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL:
case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL:
case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
assert(src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM &&
src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM &&
@@ -950,6 +959,9 @@ fs_inst::size_read(int arg) const
case SHADER_OPCODE_LOD:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_TG4_BIAS:
case SHADER_OPCODE_TG4_EXPLICIT_LOD:
case SHADER_OPCODE_TG4_IMPLICIT_LOD:
case SHADER_OPCODE_SAMPLEINFO:
if (arg == 0 && src[0].file == VGRF)
return mlen * REG_SIZE;
@@ -1080,6 +1092,9 @@ fs_inst::implied_mrf_writes() const
case SHADER_OPCODE_TXF_MCS:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_TG4_BIAS:
case SHADER_OPCODE_TG4_EXPLICIT_LOD:
case SHADER_OPCODE_TG4_IMPLICIT_LOD:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:
@@ -1115,6 +1130,9 @@ fs_inst::has_sampler_residency() const
case SHADER_OPCODE_TXS_LOGICAL:
case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
case SHADER_OPCODE_TG4_LOGICAL:
case SHADER_OPCODE_TG4_BIAS_LOGICAL:
case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL:
case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL:
assert(src[TEX_LOGICAL_SRC_RESIDENCY].file == IMM);
return src[TEX_LOGICAL_SRC_RESIDENCY].ud != 0;
default: