From 7983c6c14d4964cee89f7375a6fb117a366fc6f9 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Wed, 24 Jul 2024 13:22:31 -0400
Subject: [PATCH] ir3: switch to derivative intrinsics

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30569>
---
 src/freedreno/ir3/ir3_compiler.c     |  2 ++
 src/freedreno/ir3/ir3_compiler_nir.c | 53 ++++++++++++++--------------
 2 files changed, 28 insertions(+), 27 deletions(-)

diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c
index ae7abb3472b..b068608cf2f 100644
--- a/src/freedreno/ir3/ir3_compiler.c
+++ b/src/freedreno/ir3/ir3_compiler.c
@@ -129,6 +129,8 @@ static const nir_shader_compiler_options ir3_base_options = {
    .lower_doubles_options = (nir_lower_doubles_options)~0,
 
    .divergence_analysis_options = nir_divergence_uniform_load_tears,
+   .has_ddx_intrinsics = true,
+   .scalarize_ddx = true,
 };
 
 struct ir3_compiler *
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 6c5987c4b55..b32ba1aae78 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -467,13 +467,6 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
 
    bool use_shared = !alu->def.divergent &&
       ctx->compiler->has_scalar_alu &&
-      /* not ALU ops */
-      alu->op != nir_op_fddx &&
-      alu->op != nir_op_fddx_fine &&
-      alu->op != nir_op_fddx_coarse &&
-      alu->op != nir_op_fddy &&
-      alu->op != nir_op_fddy_fine &&
-      alu->op != nir_op_fddy_coarse &&
       /* it probably isn't worth emulating these with scalar-only ops */
       alu->op != nir_op_udot_4x8_uadd &&
       alu->op != nir_op_udot_4x8_uadd_sat &&
@@ -635,25 +628,6 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
    case nir_op_ffma:
       dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
       break;
-   case nir_op_fddx:
-   case nir_op_fddx_coarse:
-      dst[0] = ir3_DSX(b, src[0], 0);
-      dst[0]->cat5.type = TYPE_F32;
-      break;
-   case nir_op_fddx_fine:
-      dst[0] = ir3_DSXPP_MACRO(b, src[0], 0);
-      dst[0]->cat5.type = TYPE_F32;
-      break;
-   case nir_op_fddy:
-   case nir_op_fddy_coarse:
-      dst[0] = ir3_DSY(b, src[0], 0);
-      dst[0]->cat5.type = TYPE_F32;
-      break;
-      break;
-   case nir_op_fddy_fine:
-      dst[0] = ir3_DSYPP_MACRO(b, src[0], 0);
-      dst[0]->cat5.type = TYPE_F32;
-      break;
    case nir_op_flt:
       dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
       dst[0]->cat2.condition = IR3_COND_LT;
@@ -2996,7 +2970,32 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
       dst[0]->cat5.type = type_uint_size(intr->def.bit_size);
       break;
    }
-
+   case nir_intrinsic_ddx:
+   case nir_intrinsic_ddx_coarse: {
+      struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
+      dst[0] = ir3_DSX(b, src, 0);
+      dst[0]->cat5.type = TYPE_F32;
+      break;
+   }
+   case nir_intrinsic_ddx_fine: {
+      struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
+      dst[0] = ir3_DSXPP_MACRO(b, src, 0);
+      dst[0]->cat5.type = TYPE_F32;
+      break;
+   }
+   case nir_intrinsic_ddy:
+   case nir_intrinsic_ddy_coarse: {
+      struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
+      dst[0] = ir3_DSY(b, src, 0);
+      dst[0]->cat5.type = TYPE_F32;
+      break;
+   }
+   case nir_intrinsic_ddy_fine: {
+      struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
+      dst[0] = ir3_DSYPP_MACRO(b, src, 0);
+      dst[0]->cat5.type = TYPE_F32;
+      break;
+   }
    case nir_intrinsic_load_shared_ir3:
       emit_intrinsic_load_shared_ir3(ctx, intr, dst);
       break;