From 797150c144ef24bed0d6dc8adbc22a27965193c4 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 5 Aug 2022 16:34:30 +0100 Subject: [PATCH] nir/lower_tex: ignore width of cube textures On AMD hardware, height is faster to access and we're already doing so. Signed-off-by: Rhys Perry Reviewed-by: Georg Lehmann Part-of: --- src/compiler/nir/nir_lower_tex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c index 9add854736a..634384fdb41 100644 --- a/src/compiler/nir/nir_lower_tex.c +++ b/src/compiler/nir/nir_lower_tex.c @@ -1254,7 +1254,7 @@ nir_lower_txs_cube_array(nir_builder *b, nir_tex_instr *tex) assert(tex->dest.is_ssa); assert(tex->dest.ssa.num_components == 3); nir_ssa_def *size = &tex->dest.ssa; - size = nir_vec3(b, nir_channel(b, size, 0), + size = nir_vec3(b, nir_channel(b, size, 1), nir_channel(b, size, 1), nir_idiv(b, nir_channel(b, size, 2), nir_imm_int(b, 6)));