diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c
index dbe283a2d57..d9e90c749cd 100644
--- a/src/compiler/nir/nir_divergence_analysis.c
+++ b/src/compiler/nir/nir_divergence_analysis.c
@@ -765,7 +765,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
    case nir_intrinsic_load_frag_offset_ir3:
    case nir_intrinsic_bindless_resource_ir3:
    case nir_intrinsic_ray_intersection_ir3:
-   case nir_intrinsic_read_attribute_payload_intel:
+   case nir_intrinsic_load_attribute_payload_intel:
    case nir_intrinsic_load_urb_vec4_intel:
    case nir_intrinsic_load_urb_lsc_intel:
    case nir_intrinsic_load_buffer_ptr_kk:
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py
index 6de62361335..995a021b542 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -2425,7 +2425,7 @@ system_value("max_polygon_intel", 1, bit_sizes=[32])
 
 # Read the attribute thread payload at a given offset
 # src[] = { offset }
-intrinsic("read_attribute_payload_intel", dest_comp=1, bit_sizes=[32],
+intrinsic("load_attribute_payload_intel", dest_comp=1, bit_sizes=[32],
           src_comp=[1],
           flags=[CAN_ELIMINATE, CAN_REORDER])
 
diff --git a/src/intel/compiler/brw/brw_compile_fs.cpp b/src/intel/compiler/brw/brw_compile_fs.cpp
index 06e23a946d8..b0430168636 100644
--- a/src/intel/compiler/brw/brw_compile_fs.cpp
+++ b/src/intel/compiler/brw/brw_compile_fs.cpp
@@ -1299,7 +1299,7 @@ brw_assign_urb_setup(brw_shader &s)
     * setup regs, now that the location of the constants has been chosen.
     */
    foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) {
-      if (inst->opcode == FS_OPCODE_READ_ATTRIBUTE_PAYLOAD) {
+      if (inst->opcode == SHADER_OPCODE_LOAD_ATTRIBUTE_PAYLOAD) {
          brw_reg offset = inst->src[0];
          inst = brw_transform_inst(s, inst, SHADER_OPCODE_MOV_INDIRECT, 3);
          inst->src[0] = retype(brw_vec8_grf(urb_start, 0), BRW_TYPE_UD);
diff --git a/src/intel/compiler/brw/brw_eu_defines.h b/src/intel/compiler/brw/brw_eu_defines.h
index 0f23c852d16..da7c3812562 100644
--- a/src/intel/compiler/brw/brw_eu_defines.h
+++ b/src/intel/compiler/brw/brw_eu_defines.h
@@ -495,7 +495,8 @@ enum ENUM_PACKED opcode {
    FS_OPCODE_INTERPOLATE_AT_SAMPLE,
    FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
    FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
-   FS_OPCODE_READ_ATTRIBUTE_PAYLOAD,
+
+   SHADER_OPCODE_LOAD_ATTRIBUTE_PAYLOAD,
 
    /**
     * GLSL barrier()
diff --git a/src/intel/compiler/brw/brw_from_nir.cpp b/src/intel/compiler/brw/brw_from_nir.cpp
index 047084b6881..b704a61e7b5 100644
--- a/src/intel/compiler/brw/brw_from_nir.cpp
+++ b/src/intel/compiler/brw/brw_from_nir.cpp
@@ -4528,11 +4528,11 @@ brw_from_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
               brw_dynamic_per_primitive_remap(brw_wm_prog_data(s.prog_data)));
       break;
 
-   case nir_intrinsic_read_attribute_payload_intel: {
+   case nir_intrinsic_load_attribute_payload_intel: {
       const brw_reg offset = retype(
          bld.emit_uniformize(get_nir_src(ntb, instr->src[0], 0)),
          BRW_TYPE_UD);
-      bld.emit(FS_OPCODE_READ_ATTRIBUTE_PAYLOAD, retype(dest, BRW_TYPE_UD), offset);
+      bld.emit(SHADER_OPCODE_LOAD_ATTRIBUTE_PAYLOAD, retype(dest, BRW_TYPE_UD), offset);
       break;
    }
 
diff --git a/src/intel/compiler/brw/brw_lower_simd_width.cpp b/src/intel/compiler/brw/brw_lower_simd_width.cpp
index b2bb76fb536..2ce0a0a037f 100644
--- a/src/intel/compiler/brw/brw_lower_simd_width.cpp
+++ b/src/intel/compiler/brw/brw_lower_simd_width.cpp
@@ -396,7 +396,7 @@ brw_get_lowered_simd_width(const brw_shader *shader, const brw_inst *inst)
               get_fpu_lowered_simd_width(shader, inst));
    }
    case SHADER_OPCODE_MOV_INDIRECT:
-   case FS_OPCODE_READ_ATTRIBUTE_PAYLOAD: {
+   case SHADER_OPCODE_LOAD_ATTRIBUTE_PAYLOAD: {
       /* From IVB and HSW PRMs:
        *
        * "2.When the destination requires two registers and the sources are
diff --git a/src/intel/compiler/brw/brw_nir.c b/src/intel/compiler/brw/brw_nir.c
index c23024568e1..05a90495a64 100644
--- a/src/intel/compiler/brw/brw_nir.c
+++ b/src/intel/compiler/brw/brw_nir.c
@@ -983,7 +983,7 @@ brw_nir_lower_fs_inputs(nir_shader *nir,
          nir_ieq_imm(b, index, INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_MESH),
          nir_imm_int(b, 0), per_vertex_offset);
       indirect_primitive_id =
-         nir_read_attribute_payload_intel(b, attribute_offset);
+         nir_load_attribute_payload_intel(b, attribute_offset);
    }
 
    nir_foreach_shader_in_variable(var, nir) {
diff --git a/src/intel/compiler/brw/brw_nir_wa_18019110168.c b/src/intel/compiler/brw/brw_nir_wa_18019110168.c
index 4408061e755..cfa785b2419 100644
--- a/src/intel/compiler/brw/brw_nir_wa_18019110168.c
+++ b/src/intel/compiler/brw/brw_nir_wa_18019110168.c
@@ -603,7 +603,7 @@ brw_nir_frag_convert_attrs_prim_to_vert_indirect(struct nir_shader *nir,
                   brw_nir_vertex_attribute_offset(b, attr_idx, devinfo),
                   per_primitive_stride);
             nir_def *value =
-               nir_read_attribute_payload_intel(b, per_vertex_offset);
+               nir_load_attribute_payload_intel(b, per_vertex_offset);
             /* Write back the values into the per-primitive location */
             nir_store_per_primitive_payload_intel(
                b, value, .base = location, .component = c);
diff --git a/src/intel/compiler/brw/brw_print.cpp b/src/intel/compiler/brw/brw_print.cpp
index 53399e89cda..737bd0886ca 100644
--- a/src/intel/compiler/brw/brw_print.cpp
+++ b/src/intel/compiler/brw/brw_print.cpp
@@ -206,8 +206,9 @@ brw_instruction_name(const struct brw_isa_info *isa, const brw_inst *inst)
       return "interp_shared_offset";
    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
       return "interp_per_slot_offset";
-   case FS_OPCODE_READ_ATTRIBUTE_PAYLOAD:
-      return "fs_read_attribute_payload";
+
+   case SHADER_OPCODE_LOAD_ATTRIBUTE_PAYLOAD:
+      return "load_attribute_payload";
 
    case SHADER_OPCODE_BARRIER:
       return "barrier";