From 78c843230c10c93a4319bcbd0ebd096d98906900 Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Fri, 15 Dec 2023 16:37:14 +0100 Subject: [PATCH] tu/a750: Consider vertex attr buff in gmem allocation A750 added a new optimization - placement of vertex attributes into GMEM, so part of GMEM is carved out for it and needs to be considered during GMEM allocations. Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/common/freedreno_dev_info.h | 5 ++++ src/freedreno/common/freedreno_devices.py | 7 +++--- src/freedreno/vulkan/tu_cmd_buffer.cc | 30 ++++++++++++++++++++--- src/freedreno/vulkan/tu_device.cc | 30 ++++++++++++++++++++--- src/freedreno/vulkan/tu_device.h | 7 ++++++ src/freedreno/vulkan/tu_pass.cc | 2 +- 6 files changed, 70 insertions(+), 11 deletions(-) diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h index 462d372c730..fd1a675df99 100644 --- a/src/freedreno/common/freedreno_dev_info.h +++ b/src/freedreno/common/freedreno_dev_info.h @@ -215,6 +215,11 @@ struct fd_dev_info { bool load_inline_uniforms_via_preamble_ldgk; bool load_shader_consts_via_preamble; + + bool has_gmem_vpc_attr_buf; + /* Size of buffer in gmem for VPC attributes */ + uint32_t sysmem_vpc_attr_buf_size; + uint32_t gmem_vpc_attr_buf_size; } a7xx; }; diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index 89e266a6a38..68ae7f1f668 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -796,6 +796,9 @@ a7xx_750 = A7XXProps( has_event_write_sample_count = True, load_inline_uniforms_via_preamble_ldgk = True, load_shader_consts_via_preamble = True, + has_gmem_vpc_attr_buf = True, + sysmem_vpc_attr_buf_size = 0x20000, + gmem_vpc_attr_buf_size = 0xc000, ) a730_magic_regs = dict( @@ -993,10 +996,6 @@ add_gpus([ [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800B, 0x00000000], [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_800C, 0x00000000], - [A6XXRegs.REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM, 0x00020000], - [A6XXRegs.REG_A7XX_VPC_ATTR_BUF_BASE_GMEM, 0x00240000], - [A6XXRegs.REG_A7XX_PC_ATTR_BUF_SIZE_GMEM, 0x00020000], - [0x930a, 0], [0x960a, 1], [A6XXRegs.REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL, 0], diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index c549be300f1..8c62dd4d834 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -247,7 +247,14 @@ emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem) uint32_t color_offset_hi = color_offset >> 21; color_offset &= 0x1fffff; - enum a6xx_ccu_cache_size cache_size = + + uint32_t depth_offset = gmem ? 0 + : dev->physical_device->ccu_depth_offset_bypass; + + uint32_t depth_offset_hi = depth_offset >> 21; + depth_offset &= 0x1fffff; + + enum a6xx_ccu_cache_size cache_size = !gmem ? CCU_CACHE_SIZE_FULL : (a6xx_ccu_cache_size)(dev->physical_device->info->a6xx.gmem_ccu_color_cache_fraction); bool concurrent_resolve = dev->physical_device->info->a6xx.concurrent_resolve; @@ -258,13 +265,30 @@ emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem) .concurrent_resolve = concurrent_resolve, )); tu_cs_emit_regs(cs, A7XX_RB_CCU_CNTL2( - .depth_offset_hi = 0, + .depth_offset_hi = depth_offset_hi, .color_offset_hi = color_offset_hi, .depth_cache_size = CCU_CACHE_SIZE_FULL, - .depth_offset = 0, + .depth_offset = depth_offset, .color_cache_size = cache_size, .color_offset = color_offset )); + + if (dev->physical_device->info->a7xx.has_gmem_vpc_attr_buf) { + tu_cs_emit_regs(cs, + A7XX_VPC_ATTR_BUF_SIZE_GMEM( + .size_gmem = + gmem ? dev->physical_device->vpc_attr_buf_size_gmem + : dev->physical_device->vpc_attr_buf_size_bypass), + A7XX_VPC_ATTR_BUF_BASE_GMEM( + .base_gmem = + gmem ? dev->physical_device->vpc_attr_buf_offset_gmem + : dev->physical_device->vpc_attr_buf_offset_bypass), ); + tu_cs_emit_regs(cs, + A7XX_PC_ATTR_BUF_SIZE_GMEM( + .size_gmem = + gmem ? dev->physical_device->vpc_attr_buf_size_gmem + : dev->physical_device->vpc_attr_buf_size_bypass), ); + } } else { tu_cs_emit_regs(cs, A6XX_RB_CCU_CNTL( .gmem_fast_clear_disable = diff --git a/src/freedreno/vulkan/tu_device.cc b/src/freedreno/vulkan/tu_device.cc index db7d06062d2..61a7586c28b 100644 --- a/src/freedreno/vulkan/tu_device.cc +++ b/src/freedreno/vulkan/tu_device.cc @@ -641,11 +641,35 @@ tu_physical_device_init(struct tu_physical_device *device, device->info->num_ccu * device->info->a6xx.sysmem_per_ccu_depth_cache_size; uint32_t color_cache_size = (device->info->num_ccu * - device->info->a6xx.sysmem_per_ccu_color_cache_size) / + device->info->a6xx.sysmem_per_ccu_color_cache_size); + uint32_t color_cache_size_gmem = + color_cache_size / (1 << device->info->a6xx.gmem_ccu_color_cache_fraction); - device->ccu_offset_bypass = depth_cache_size; - device->ccu_offset_gmem = device->gmem_size - color_cache_size; + device->ccu_depth_offset_bypass = 0; + device->ccu_offset_bypass = + device->ccu_depth_offset_bypass + depth_cache_size; + + if (device->info->a7xx.has_gmem_vpc_attr_buf) { + device->vpc_attr_buf_size_bypass = + device->info->a7xx.sysmem_vpc_attr_buf_size; + device->vpc_attr_buf_offset_bypass = + device->ccu_offset_bypass + color_cache_size; + + device->vpc_attr_buf_size_gmem = + device->info->a7xx.gmem_vpc_attr_buf_size; + device->vpc_attr_buf_offset_gmem = + device->gmem_size - + (device->vpc_attr_buf_size_gmem * device->info->num_ccu); + + device->ccu_offset_gmem = + device->vpc_attr_buf_offset_gmem - color_cache_size_gmem; + + device->usable_gmem_size_gmem = device->vpc_attr_buf_offset_gmem; + } else { + device->ccu_offset_gmem = device->gmem_size - color_cache_size_gmem; + device->usable_gmem_size_gmem = device->gmem_size; + } if (instance->reserve_descriptor_set) { device->usable_sets = device->reserved_set_idx = device->info->a6xx.max_sets - 1; diff --git a/src/freedreno/vulkan/tu_device.h b/src/freedreno/vulkan/tu_device.h index ffa680bba95..0bbbbf60883 100644 --- a/src/freedreno/vulkan/tu_device.h +++ b/src/freedreno/vulkan/tu_device.h @@ -88,8 +88,15 @@ struct tu_physical_device uint32_t gmem_size; uint64_t gmem_base; + + uint32_t usable_gmem_size_gmem; uint32_t ccu_offset_gmem; uint32_t ccu_offset_bypass; + uint32_t ccu_depth_offset_bypass; + uint32_t vpc_attr_buf_offset_gmem; + uint32_t vpc_attr_buf_size_gmem; + uint32_t vpc_attr_buf_offset_bypass; + uint32_t vpc_attr_buf_size_bypass; /* Amount of usable descriptor sets, this excludes any reserved set */ uint32_t usable_sets; diff --git a/src/freedreno/vulkan/tu_pass.cc b/src/freedreno/vulkan/tu_pass.cc index 18d22e2a973..5ed3f82f1f9 100644 --- a/src/freedreno/vulkan/tu_pass.cc +++ b/src/freedreno/vulkan/tu_pass.cc @@ -617,7 +617,7 @@ tu_render_pass_gmem_config(struct tu_render_pass *pass, * optimal: nblocks = {13, 51}, pixels = 208896 */ uint32_t gmem_size = layout == TU_GMEM_LAYOUT_FULL - ? phys_dev->gmem_size + ? phys_dev->usable_gmem_size_gmem : phys_dev->ccu_offset_gmem; uint32_t gmem_blocks = gmem_size / gmem_align; uint32_t offset = 0, pixels = ~0u, i;