From 783609a849d4f5f8ee1eb43c88a7fcf4d078ec40 Mon Sep 17 00:00:00 2001
From: Rhys Perry <pendingchaos02@gmail.com>
Date: Fri, 11 Jun 2021 13:11:20 +0100
Subject: [PATCH] aco: add RegClass::is_linear_vgpr helper
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Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12172>
---
 src/amd/compiler/aco_ir.h                    | 3 ++-
 src/amd/compiler/aco_register_allocation.cpp | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h
index 525f6c21a85..7a93be52261 100644
--- a/src/amd/compiler/aco_ir.h
+++ b/src/amd/compiler/aco_ir.h
@@ -343,11 +343,12 @@ struct RegClass {
    explicit operator bool() = delete;
 
    constexpr RegType type() const { return rc <= RC::s16 ? RegType::sgpr : RegType::vgpr; }
+   constexpr bool is_linear_vgpr() const { return rc & (1 << 6); };
    constexpr bool is_subdword() const { return rc & (1 << 7); }
    constexpr unsigned bytes() const { return ((unsigned)rc & 0x1F) * (is_subdword() ? 1 : 4); }
    // TODO: use size() less in favor of bytes()
    constexpr unsigned size() const { return (bytes() + 3) >> 2; }
-   constexpr bool is_linear() const { return rc <= RC::s16 || rc & (1 << 6); }
+   constexpr bool is_linear() const { return rc <= RC::s16 || is_linear_vgpr(); }
    constexpr RegClass as_linear() const { return RegClass((RC)(rc | (1 << 6))); }
    constexpr RegClass as_subdword() const { return RegClass((RC)(rc | 1 << 7)); }
 
diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index d57c482509f..c3d13f0bf31 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -1075,7 +1075,7 @@ get_regs_for_copies(ra_ctx& ctx, RegisterFile& reg_file,
                continue;
             }
             /* we cannot split live ranges of linear vgprs */
-            if (ctx.assignments[reg_file[j]].rc & (1 << 6)) {
+            if (ctx.assignments[reg_file[j]].rc.is_linear_vgpr()) {
                found = false;
                break;
             }
@@ -1222,7 +1222,7 @@ get_reg_impl(ra_ctx& ctx, RegisterFile& reg_file,
          }
 
          /* we cannot split live ranges of linear vgprs */
-         if (ctx.assignments[reg_file[j]].rc & (1 << 6)) {
+         if (ctx.assignments[reg_file[j]].rc.is_linear_vgpr()) {
             found = false;
             break;
          }
@@ -1679,7 +1679,7 @@ get_reg_create_vector(ra_ctx& ctx, RegisterFile& reg_file, Temp temp,
             } else {
                k += 4;
                /* we cannot split live ranges of linear vgprs */
-               if (ctx.assignments[reg_file[j]].rc & (1 << 6))
+               if (ctx.assignments[reg_file[j]].rc.is_linear_vgpr())
                   linear_vgpr = true;
             }
          }
@@ -1917,7 +1917,7 @@ Temp
 handle_live_in(ra_ctx& ctx, Temp val, Block* block)
 {
    std::vector<unsigned>& preds = val.is_linear() ? block->linear_preds : block->logical_preds;
-   if (preds.size() == 0 || val.regClass() == val.regClass().as_linear())
+   if (preds.size() == 0 || val.regClass().is_linear_vgpr())
       return val;
 
    if (preds.size() == 1) {