From 77e1fc67bc755c4685117aa24d3575903d42330e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 27 Apr 2022 02:30:49 -0400 Subject: [PATCH] radeonsi: align the tessellation ring address to 2MB Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_state_shaders.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index ff9003106b7..249cd5ff687 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -3944,11 +3944,11 @@ void si_init_tess_factor_ring(struct si_context *sctx) assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0); /* The address must be aligned to 2^19, because the shader only - * receives the high 13 bits. + * receives the high 13 bits. Align it to 2MB to match the GPU page size. */ sctx->tess_rings = pipe_aligned_buffer_create( sctx->b.screen, SI_RESOURCE_FLAG_32BIT | SI_RESOURCE_FLAG_DRIVER_INTERNAL, PIPE_USAGE_DEFAULT, - sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, 1 << 19); + sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, 2 * 1024 * 1024); if (!sctx->tess_rings) return; @@ -3957,7 +3957,7 @@ void si_init_tess_factor_ring(struct si_context *sctx) sctx->b.screen, PIPE_RESOURCE_FLAG_ENCRYPTED | SI_RESOURCE_FLAG_32BIT | SI_RESOURCE_FLAG_DRIVER_INTERNAL, PIPE_USAGE_DEFAULT, - sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, 1 << 19); + sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, 2 * 1024 * 1024); } uint64_t factor_va =