diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
index 2c2febdb24e..26a4d4c887b 100644
--- a/src/amd/common/ac_shader_util.c
+++ b/src/amd/common/ac_shader_util.c
@@ -888,23 +888,6 @@ unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_
       unreachable("invalid LSHS shader stage");
 }
 
-unsigned ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size,
-                                        unsigned es_verts, unsigned gs_inst_prims)
-{
-   /* ESGS may operate in workgroups if on-chip GS (LDS rings) are enabled.
-    *
-    * GFX6: Not possible in the HW.
-    * GFX7-8 (unmerged): possible in the HW, but not implemented in Mesa.
-    * GFX9+ (merged): implemented in Mesa.
-    */
-
-   if (gfx_level <= GFX8)
-      return wave_size;
-
-   unsigned workgroup_size = MAX2(es_verts, gs_inst_prims);
-   return CLAMP(workgroup_size, 1, 256);
-}
-
 unsigned ac_compute_ngg_workgroup_size(unsigned es_verts, unsigned gs_inst_prims,
                                        unsigned max_vtx_out, unsigned prim_amp_factor)
 {
diff --git a/src/amd/common/ac_shader_util.h b/src/amd/common/ac_shader_util.h
index 63952e6a871..184b26848d4 100644
--- a/src/amd/common/ac_shader_util.h
+++ b/src/amd/common/ac_shader_util.h
@@ -287,9 +287,6 @@ unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_
                                         unsigned tess_patch_in_vtx,
                                         unsigned tess_patch_out_vtx);
 
-unsigned ac_compute_esgs_workgroup_size(enum amd_gfx_level gfx_level, unsigned wave_size,
-                                        unsigned es_verts, unsigned gs_inst_prims);
-
 unsigned ac_compute_ngg_workgroup_size(unsigned es_verts, unsigned gs_inst_prims,
                                        unsigned max_vtx_out, unsigned prim_amp_factor);
 
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index 8c0f94c784b..2b7e95d85dc 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -1265,11 +1265,20 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
       break;
    case MESA_SHADER_GEOMETRY:
       if (!info->is_ngg) {
-         unsigned es_verts_per_subgroup = info->gs_ring_info.es_verts_per_subgroup;
-         unsigned gs_inst_prims_in_subgroup = info->gs_ring_info.gs_inst_prims_in_subgroup;
+         /* ESGS may operate in workgroups if on-chip GS (LDS rings) are enabled.
+          *
+          * GFX6: Not possible in the HW.
+          * GFX7-8 (unmerged): possible in the HW, but not implemented in Mesa.
+          * GFX9+ (merged): implemented in Mesa.
+          *
+          * Set the maximum possible value by default, this will be optimized during linking if
+          * possible.
+          */
+         if (pdev->info.gfx_level <= GFX8)
+            info->workgroup_size = info->wave_size;
+         else
+            info->workgroup_size = 256;
 
-         info->workgroup_size = ac_compute_esgs_workgroup_size(pdev->info.gfx_level, info->wave_size,
-                                                               es_verts_per_subgroup, gs_inst_prims_in_subgroup);
       } else {
          /* Set the maximum possible value by default, this will be optimized during linking if
           * possible.