gallium: Rename MUL_ZERO_WINS to LEGACY_MATH_RULES.

This is a clearer name for what it does than MUL_ZERO_WINS, and matches up to the new name in shader_info. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16176>
2022-06-02 11:59:37 -07:00
parent cf265c6606
commit 76b203eb39
13 changed files with 19 additions and 19 deletions
@@ -160,7 +160,7 @@ const char *tgsi_property_names[TGSI_PROPERTY_COUNT] =
   "CS_FIXED_BLOCK_WIDTH",
   "CS_FIXED_BLOCK_HEIGHT",
   "CS_FIXED_BLOCK_DEPTH",
-   "MUL_ZERO_WINS",
+   "LEGACY_MATH_RULES",
   "VS_BLIT_SGPRS_AMD",
   "CS_USER_DATA_COMPONENTS_AMD",
   "LAYER_VIEWPORT_RELATIVE",
@@ -307,7 +307,7 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
   case PIPE_CAP_FBFETCH:
   case PIPE_CAP_FBFETCH_COHERENT:
   case PIPE_CAP_BLEND_EQUATION_ADVANCED:
-   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
   case PIPE_CAP_DOUBLES:
   case PIPE_CAP_INT64:
   case PIPE_CAP_INT64_DIVMOD:
@@ -218,7 +218,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
   case PIPE_CAP_SHADER_CAN_READ_OUTPUTS:
   case PIPE_CAP_NATIVE_FENCE_FD:
   case PIPE_CAP_FBFETCH:
-   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
   case PIPE_CAP_DOUBLES:
   case PIPE_CAP_INT64:
   case PIPE_CAP_INT64_DIVMOD:
@@ -248,7 +248,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
   case PIPE_CAP_STRING_MARKER:
   case PIPE_CAP_CULL_DISTANCE:
   case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
-   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
   case PIPE_CAP_TGSI_TEX_TXF_LZ:
   case PIPE_CAP_SHADER_CLOCK:
   case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
@@ -288,7 +288,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
   case PIPE_CAP_SHADER_GROUP_VOTE:
   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
   case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
-   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+   case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
   case PIPE_CAP_DOUBLES:
   case PIPE_CAP_INT64:
   case PIPE_CAP_TGSI_TEX_TXF_LZ:
@@ -312,7 +312,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 	case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 	case PIPE_CAP_CLEAR_TEXTURE:
-	case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+	case PIPE_CAP_TGSI_LEGACY_MATH_RULES:
 	case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 	case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 	case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
@@ -4721,7 +4721,7 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap, int trans_only)
 	unsigned op = ctx->inst_info->op;

 	if (op == ALU_OP2_MUL_IEEE &&
-	    ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
+	    ctx->info.properties[TGSI_PROPERTY_LEGACY_MATH_RULES])
 		op = ALU_OP2_MUL;

 	/* nir_to_tgsi lowers nir_op_isub to UADD + negate, since r600 doesn't support
@@ -7305,7 +7305,7 @@ static int tgsi_op3_dst(struct r600_shader_ctx *ctx, int dst)
 	unsigned op = ctx->inst_info->op;

 	if (op == ALU_OP3_MULADD_IEEE &&
-	    ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
+	    ctx->info.properties[TGSI_PROPERTY_LEGACY_MATH_RULES])
 		op = ALU_OP3_MULADD;

 	for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
@@ -7355,7 +7355,7 @@ static int tgsi_dp(struct r600_shader_ctx *ctx)
 	int i, j, r;
 	unsigned op = ctx->inst_info->op;
 	if (op == ALU_OP2_DOT4_IEEE &&
-	    ctx->info.properties[TGSI_PROPERTY_MUL_ZERO_WINS])
+	    ctx->info.properties[TGSI_PROPERTY_LEGACY_MATH_RULES])
 		op = ALU_OP2_DOT4;

 	for (i = 0; i < 4; i++) {
@@ -3666,9 +3666,9 @@ tx_ctor(struct shader_translator *tx, struct pipe_screen *screen, struct nine_sh
            ureg_property(tx->ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER, TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
    }

-    tx->mul_zero_wins = GET_CAP(TGSI_MUL_ZERO_WINS);
+    tx->mul_zero_wins = GET_CAP(TGSI_LEGACY_MATH_RULES);
    if (tx->mul_zero_wins)
-       ureg_property(tx->ureg, TGSI_PROPERTY_MUL_ZERO_WINS, 1);
+       ureg_property(tx->ureg, TGSI_PROPERTY_LEGACY_MATH_RULES, 1);

    /* Add additional definition of constants */
    if (info->add_constants_defs.c_combination) {
@@ -3894,7 +3894,7 @@ nine_ureg_create_shader(struct ureg_program                  *ureg,
    enum pipe_shader_type shader_type = ((struct tgsi_processor *) &tgsi_tokens[1])->Processor;

    /* NIR doesn't have mul_zero_wins */
-    bool ttn_supported = !GET_CAP(TGSI_MUL_ZERO_WINS);
+    bool ttn_supported = !GET_CAP(TGSI_LEGACY_MATH_RULES);
    int preferred_ir = screen->get_shader_param(screen, shader_type, PIPE_SHADER_CAP_PREFERRED_IR);
    int supported_irs = screen->get_shader_param(screen, shader_type, PIPE_SHADER_CAP_SUPPORTED_IRS);
    bool prefer_nir = (preferred_ir == PIPE_SHADER_IR_NIR);
@@ -891,7 +891,7 @@ enum pipe_cap
   PIPE_CAP_NATIVE_FENCE_FD,
   PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS,
   PIPE_CAP_FBFETCH,
-   PIPE_CAP_TGSI_MUL_ZERO_WINS,
+   PIPE_CAP_TGSI_LEGACY_MATH_RULES,
   PIPE_CAP_DOUBLES,
   PIPE_CAP_INT64,
   PIPE_CAP_INT64_DIVMOD,
@@ -298,7 +298,7 @@ enum tgsi_property_name {
   TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
   TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
   TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
-   TGSI_PROPERTY_MUL_ZERO_WINS,
+   TGSI_PROPERTY_LEGACY_MATH_RULES,
   TGSI_PROPERTY_VS_BLIT_SGPRS_AMD,
   TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD,
   TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE,
@@ -1233,7 +1233,7 @@ void Source::scanProperty(const struct tgsi_full_property *prop)
   case TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE:
      info_out->prop.fp.postDepthCoverage = prop->u[0].Data;
      break;
-   case TGSI_PROPERTY_MUL_ZERO_WINS:
+   case TGSI_PROPERTY_LEGACY_MATH_RULES:
      info->io.mul_zero_wins = prop->u[0].Data;
      break;
   case TGSI_PROPERTY_LAYER_VIEWPORT_RELATIVE: