From 764ee3a8340682263389525c4b4d4cbdcdca5ddd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Thu, 26 Jun 2025 17:36:16 +0200 Subject: [PATCH] radv: don't lower subdword phis to scalar Totals from 193 (0.24% of 79839) affected shaders: (Navi48) MaxWaves: 6004 -> 6024 (+0.33%) Instrs: 169276 -> 166784 (-1.47%); split: -3.01%, +1.53% CodeSize: 940608 -> 915768 (-2.64%); split: -4.29%, +1.64% VGPRs: 8012 -> 7716 (-3.69%); split: -3.99%, +0.30% SpillVGPRs: 185 -> 0 (-inf%) Scratch: 13568 -> 0 (-inf%) Latency: 2159787 -> 2147084 (-0.59%); split: -2.86%, +2.28% InvThroughput: 664022 -> 395859 (-40.38%); split: -42.59%, +2.21% VClause: 2998 -> 2880 (-3.94%); split: -4.27%, +0.33% SClause: 3117 -> 3120 (+0.10%) Copies: 21290 -> 16278 (-23.54%); split: -24.74%, +1.20% Branches: 4757 -> 4760 (+0.06%); split: -0.34%, +0.40% PreSGPRs: 7369 -> 7378 (+0.12%); split: -0.11%, +0.23% PreVGPRs: 4257 -> 3859 (-9.35%); split: -9.94%, +0.59% VALU: 83173 -> 79804 (-4.05%); split: -5.68%, +1.63% SALU: 36672 -> 37318 (+1.76%); split: -0.02%, +1.78% VMEM: 4012 -> 3762 (-6.23%); split: -6.83%, +0.60% SMEM: 4300 -> 4303 (+0.07%) Part-of: --- src/amd/common/nir/ac_nir.c | 10 ++++++++++ src/amd/common/nir/ac_nir.h | 3 +++ src/amd/common/nir/ac_nir_lower_ngg.c | 2 +- src/amd/common/nir/ac_nir_lower_ngg_mesh.c | 2 +- src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c | 2 +- .../compiler/instruction_selection/aco_isel_setup.cpp | 2 +- src/amd/vulkan/radv_shader.c | 2 +- 7 files changed, 18 insertions(+), 5 deletions(-) diff --git a/src/amd/common/nir/ac_nir.c b/src/amd/common/nir/ac_nir.c index 52911038ae0..264525f55f4 100644 --- a/src/amd/common/nir/ac_nir.c +++ b/src/amd/common/nir/ac_nir.c @@ -879,3 +879,13 @@ ac_nir_repack_invocations_in_workgroup(nir_builder *b, nir_def **input_bool, nir_mbcnt_amd(b, input_mask[i], wg_repacked_index_base); } } + +uint8_t +ac_nir_lower_phis_to_scalar_cb(const nir_instr *instr, const void *_) +{ + nir_phi_instr *phi = nir_instr_as_phi(instr); + if (phi->def.bit_size == 1 || phi->def.bit_size >= 32) + return 1; + + return 32 / phi->def.bit_size; +} diff --git a/src/amd/common/nir/ac_nir.h b/src/amd/common/nir/ac_nir.h index b2e6242b420..0c7166b4749 100644 --- a/src/amd/common/nir/ac_nir.h +++ b/src/amd/common/nir/ac_nir.h @@ -434,6 +434,9 @@ ac_nir_scalarize_overfetching_loads_callback(const nir_instr *instr, const void enum gl_access_qualifier ac_nir_get_mem_access_flags(const nir_intrinsic_instr *instr); +uint8_t +ac_nir_lower_phis_to_scalar_cb(const nir_instr *instr, const void *_); + #ifdef __cplusplus } #endif diff --git a/src/amd/common/nir/ac_nir_lower_ngg.c b/src/amd/common/nir/ac_nir_lower_ngg.c index 033e756be9d..28107ca5978 100644 --- a/src/amd/common/nir/ac_nir_lower_ngg.c +++ b/src/amd/common/nir/ac_nir_lower_ngg.c @@ -1797,7 +1797,7 @@ ac_nir_lower_ngg_nogs(nir_shader *shader, const ac_nir_lower_ngg_options *option nir_lower_vars_to_ssa(shader); nir_remove_dead_variables(shader, nir_var_function_temp, NULL); nir_lower_alu_to_scalar(shader, NULL, NULL); - nir_lower_all_phis_to_scalar(shader); + nir_lower_phis_to_scalar(shader, ac_nir_lower_phis_to_scalar_cb, NULL); if (options->can_cull) { /* It's beneficial to redo these opts after splitting the shader. */ diff --git a/src/amd/common/nir/ac_nir_lower_ngg_mesh.c b/src/amd/common/nir/ac_nir_lower_ngg_mesh.c index 02967f27cad..84a7adbfd51 100644 --- a/src/amd/common/nir/ac_nir_lower_ngg_mesh.c +++ b/src/amd/common/nir/ac_nir_lower_ngg_mesh.c @@ -1429,7 +1429,7 @@ ac_nir_lower_ngg_mesh(nir_shader *shader, nir_lower_vars_to_ssa(shader); nir_remove_dead_variables(shader, nir_var_function_temp, NULL); nir_lower_alu_to_scalar(shader, NULL, NULL); - nir_lower_all_phis_to_scalar(shader); + nir_lower_phis_to_scalar(shader, ac_nir_lower_phis_to_scalar_cb, NULL); /* Optimize load_local_invocation_index. When the API workgroup is smaller than the HW workgroup, * local_invocation_id isn't initialized for all lanes and we can't perform this optimization for diff --git a/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c index 7a160023a17..a542cdecac2 100644 --- a/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c @@ -1624,7 +1624,7 @@ ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, const nir_tcs_info *info, NIR_PASS(_, shader, nir_lower_vars_to_ssa); NIR_PASS(_, shader, nir_remove_dead_variables, nir_var_function_temp, NULL); NIR_PASS(_, shader, nir_lower_alu_to_scalar, NULL, NULL); - NIR_PASS(_, shader, nir_lower_all_phis_to_scalar); + NIR_PASS(_, shader, nir_lower_phis_to_scalar, ac_nir_lower_phis_to_scalar_cb, NULL); return true; } diff --git a/src/amd/compiler/instruction_selection/aco_isel_setup.cpp b/src/amd/compiler/instruction_selection/aco_isel_setup.cpp index 254a70d7928..b3623f92a15 100644 --- a/src/amd/compiler/instruction_selection/aco_isel_setup.cpp +++ b/src/amd/compiler/instruction_selection/aco_isel_setup.cpp @@ -249,7 +249,7 @@ void setup_nir(isel_context* ctx, nir_shader* nir) { nir_convert_to_lcssa(nir, true, false); - if (nir_lower_all_phis_to_scalar(nir)) { + if (nir_lower_phis_to_scalar(nir, ac_nir_lower_phis_to_scalar_cb, NULL)) { nir_copy_prop(nir); nir_opt_dce(nir); } diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 28d1335c25e..0a713e499ff 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -181,7 +181,7 @@ radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively) NIR_LOOP_PASS(_, skip, shader, nir_lower_vars_to_ssa); NIR_LOOP_PASS(_, skip, shader, nir_lower_alu_width, vectorize_vec2_16bit, NULL); - NIR_LOOP_PASS(_, skip, shader, nir_lower_all_phis_to_scalar); + NIR_LOOP_PASS(_, skip, shader, nir_lower_phis_to_scalar, ac_nir_lower_phis_to_scalar_cb, NULL); NIR_LOOP_PASS(progress, skip, shader, nir_copy_prop); NIR_LOOP_PASS(progress, skip, shader, nir_opt_remove_phis);