diff --git a/src/amd/common/nir/ac_nir.h b/src/amd/common/nir/ac_nir.h
index 08498d6c4dd..c3abe33bdec 100644
--- a/src/amd/common/nir/ac_nir.h
+++ b/src/amd/common/nir/ac_nir.h
@@ -202,9 +202,6 @@ typedef struct {
    bool export_primitive_id_per_prim;
    uint32_t instance_rate_inputs;
    uint32_t user_clip_plane_enable_mask;
-
-   /* GS */
-   unsigned gs_out_vtx_bytes;
 } ac_nir_lower_ngg_options;
 
 bool
@@ -212,7 +209,8 @@ ac_nir_lower_ngg_nogs(nir_shader *shader, const ac_nir_lower_ngg_options *option
                       uint32_t *out_lds_vertex_size);
 
 bool
-ac_nir_lower_ngg_gs(nir_shader *shader, const ac_nir_lower_ngg_options *options);
+ac_nir_lower_ngg_gs(nir_shader *shader, const ac_nir_lower_ngg_options *options,
+                    uint32_t *out_lds_vertex_size);
 
 bool
 ac_nir_lower_ngg_mesh(nir_shader *shader,
diff --git a/src/amd/common/nir/ac_nir_lower_ngg_gs.c b/src/amd/common/nir/ac_nir_lower_ngg_gs.c
index 9a650d3f7c1..0a4e8fcb575 100644
--- a/src/amd/common/nir/ac_nir_lower_ngg_gs.c
+++ b/src/amd/common/nir/ac_nir_lower_ngg_gs.c
@@ -897,17 +897,22 @@ ngg_gs_finale(nir_builder *b, lower_ngg_gs_state *s)
 }
 
 bool
-ac_nir_lower_ngg_gs(nir_shader *shader, const ac_nir_lower_ngg_options *options)
+ac_nir_lower_ngg_gs(nir_shader *shader, const ac_nir_lower_ngg_options *options,
+                    uint32_t *out_lds_vertex_size)
 {
    nir_function_impl *impl = nir_shader_get_entrypoint(shader);
    assert(impl);
 
+   /* Add 4 for primflags. */
+   *out_lds_vertex_size = (util_bitcount64(shader->info.outputs_written) +
+                           util_bitcount(shader->info.outputs_written_16bit)) * 16 + 4;
+
    lower_ngg_gs_state state = {
       .options = options,
       .impl = impl,
       .max_num_waves = DIV_ROUND_UP(options->max_workgroup_size, options->wave_size),
-      .lds_offs_primflags = options->gs_out_vtx_bytes,
-      .lds_bytes_per_gs_out_vertex = options->gs_out_vtx_bytes + 4u,
+      .lds_offs_primflags = *out_lds_vertex_size - 4,
+      .lds_bytes_per_gs_out_vertex = *out_lds_vertex_size,
       .streamout_enabled = shader->xfb_info && !options->disable_streamout,
    };
 
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index dec6dc15148..5f7422765d1 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -818,9 +818,7 @@ radv_lower_ngg(struct radv_device *device, struct radv_shader_stage *ngg_stage,
    } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
       assert(info->is_ngg);
 
-      options.gs_out_vtx_bytes = info->gs.gsvs_vertex_size;
-
-      NIR_PASS(_, nir, ac_nir_lower_ngg_gs, &options);
+      NIR_PASS(_, nir, ac_nir_lower_ngg_gs, &options, &ngg_stage->info.ngg_lds_vertex_size);
    } else if (nir->info.stage == MESA_SHADER_MESH) {
       /* ACO aligns the workgroup size to the wave size. */
       unsigned hw_workgroup_size = ALIGN(info->workgroup_size, info->wave_size);
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index f3c9f15becd..f6a150a3e4b 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -1503,7 +1503,7 @@ gfx10_get_ngg_info(const struct radv_device *device, struct radv_shader_info *es
       }
 
       esvert_lds_size = es_info->esgs_itemsize / 4;
-      gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
+      gsprim_lds_size = (gs_info->ngg_lds_vertex_size / 4) * max_out_verts_per_gsprim;
    } else {
       /* VS and TES. */
       /* LDS size for passing data from GS to ES. */
diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h
index 4f1b4e89261..f72ea8af4af 100644
--- a/src/amd/vulkan/radv_shader_info.h
+++ b/src/amd/vulkan/radv_shader_info.h
@@ -100,7 +100,7 @@ struct radv_shader_info {
    bool has_xfb_query;
    uint32_t num_tess_patches;
    uint32_t esgs_itemsize; /* Only for VS or TES as ES */
-   uint32_t ngg_lds_vertex_size;
+   uint32_t ngg_lds_vertex_size; /* VS,TES: Cull+XFB, GS: GSVS size */
    struct radv_vs_output_info outinfo;
    unsigned workgroup_size;
    bool force_vrs_per_vertex;
diff --git a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
index f9c4a0413c6..308ebb5f697 100644
--- a/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
+++ b/src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
@@ -100,7 +100,7 @@ retry_select_mode:
       }
 
       esvert_lds_size = es_sel->info.esgs_vertex_stride / 4;
-      gsprim_lds_size = (gs_sel->info.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
+      gsprim_lds_size = (shader->info.ngg_lds_vertex_size / 4) * max_out_verts_per_gsprim;
 
       if (gsprim_lds_size > target_lds_size && !force_multi_cycling) {
          if (gs_sel->tess_turns_off_ngg || es_sel->stage != MESA_SHADER_TESS_EVAL) {
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index 306e7b67f67..3d3cb489182 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1176,7 +1176,6 @@ static void si_lower_ngg(struct si_shader *shader, nir_shader *nir,
    } else {
       assert(nir->info.stage == MESA_SHADER_GEOMETRY);
 
-      options.gs_out_vtx_bytes = sel->info.gsvs_vertex_size;
       options.has_gen_prim_query = options.has_xfb_prim_query =
          sel->screen->info.gfx_level >= GFX11;
       options.has_gs_invocations_query = sel->screen->info.gfx_level < GFX11;
@@ -1186,7 +1185,7 @@ static void si_lower_ngg(struct si_shader *shader, nir_shader *nir,
       if (key->ge.part.gs.es)
          nir->info.writes_memory |= key->ge.part.gs.es->info.base.writes_memory;
 
-      NIR_PASS_V(nir, ac_nir_lower_ngg_gs, &options);
+      NIR_PASS_V(nir, ac_nir_lower_ngg_gs, &options, &shader->info.ngg_lds_vertex_size);
    }
 
    /* may generate some vector output store */
diff --git a/src/gallium/drivers/radeonsi/si_shader_info.c b/src/gallium/drivers/radeonsi/si_shader_info.c
index 6e975528bd2..5254fb0d8fc 100644
--- a/src/gallium/drivers/radeonsi/si_shader_info.c
+++ b/src/gallium/drivers/radeonsi/si_shader_info.c
@@ -637,8 +637,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, struct nir_shader *nir,
    }
 
    if (nir->info.stage == MESA_SHADER_GEOMETRY) {
-      info->gsvs_vertex_size = info->num_outputs * 16;
-      info->max_gsvs_emit_size = info->gsvs_vertex_size * nir->info.gs.vertices_out;
+      info->max_gsvs_emit_size = info->num_outputs * 16 * nir->info.gs.vertices_out;
       info->gs_input_verts_per_prim =
          mesa_vertices_per_prim(nir->info.gs.input_primitive);
    }
diff --git a/src/gallium/drivers/radeonsi/si_shader_info.h b/src/gallium/drivers/radeonsi/si_shader_info.h
index 2b03dcce7d6..47d84f5e378 100644
--- a/src/gallium/drivers/radeonsi/si_shader_info.h
+++ b/src/gallium/drivers/radeonsi/si_shader_info.h
@@ -114,7 +114,6 @@ struct si_shader_info {
    uint8_t culldist_mask;
 
    uint16_t esgs_vertex_stride;
-   uint16_t gsvs_vertex_size;
    uint8_t gs_input_verts_per_prim;
    unsigned max_gsvs_emit_size;
 
@@ -240,7 +239,7 @@ struct si_shader_variant_info {
    uint8_t num_streamout_vec4s;
    unsigned private_mem_vgprs;
    unsigned max_simd_waves;
-   uint32_t ngg_lds_vertex_size;
+   uint32_t ngg_lds_vertex_size; /* VS,TES: Cull+XFB, GS: GSVS size */
 };
 
 #endif