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i965: Add blorp support for gen4-5

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Due to complications with things such as URB setup on gen4-5, it's
easier to keep gen4 support in blorp completely internal to i965.  This
makes things a bit awkward because that means there's a file in i965
that includes blorp_priv.h but it's either that or have a file in blorp
that includes brw_context.h.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Jason Ekstrand
2016-09-09 16:30:24 -07:00
parent 23125b7102
commit 752d7af77a
10 changed files with 322 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/blorp/blorp.c
+3 -3
View File
@@ -124,10 +124,10 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
info->z_offset = 0;
}
/* Sandy Bridge has a limit of a maximum of 512 layers for layered
* rendering.
/* Sandy Bridge and earlier have a limit of a maximum of 512 layers for
* layered rendering.
*/
if (is_render_target && blorp->isl_dev->info->gen == 6)
if (is_render_target && blorp->isl_dev->info->gen <= 6)
info->view.array_len = MIN2(info->view.array_len, 512);
}
src/intel/blorp/blorp_blit.c
+12
View File
@@ -1672,6 +1672,18 @@ try_blorp_blit(struct blorp_batch *batch,
coords->y.dst0, coords->y.dst1,
coords->y.mirror);
if (devinfo->gen == 4) {
/* The MinLOD and MinimumArrayElement don't work properly for cube maps.
* Convert them to a single slice on gen4.
*/
if (params->dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)
blorp_surf_convert_to_single_slice(batch->blorp->isl_dev, &params->dst);
if (params->src.surf.usage & ISL_SURF_USAGE_CUBE_BIT)
blorp_surf_convert_to_single_slice(batch->blorp->isl_dev, &params->src);
}
if (devinfo->gen > 6 &&
params->dst.surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
assert(params->dst.surf.samples > 1);
src/intel/blorp/blorp_clear.c
+21 -5
View File
@@ -366,11 +366,6 @@ blorp_clear(struct blorp_batch *batch,
struct blorp_params params;
blorp_params_init(&params);
params.x0 = x0;
params.y0 = y0;
params.x1 = x1;
params.y1 = y1;
/* Manually apply the clear destination swizzle. This way swizzled clears
* will work for swizzles which we can't normally use for rendering and it
* also ensures that they work on pre-Haswell hardware which can't swizlle
@@ -427,6 +422,27 @@ blorp_clear(struct blorp_batch *batch,
start_layer, format, true);
params.dst.view.swizzle = swizzle;
params.x0 = x0;
params.y0 = y0;
params.x1 = x1;
params.y1 = y1;
/* The MinLOD and MinimumArrayElement don't work properly for cube maps.
* Convert them to a single slice on gen4.
*/
if (batch->blorp->isl_dev->info->gen == 4 &&
(params.dst.surf.usage & ISL_SURF_USAGE_CUBE_BIT)) {
blorp_surf_convert_to_single_slice(batch->blorp->isl_dev, &params.dst);
if (params.dst.tile_x_sa || params.dst.tile_y_sa) {
/* This is gen4 so there is no multisampling and sa == px. */
params.x0 += params.dst.tile_x_sa;
params.y0 += params.dst.tile_y_sa;
params.x1 += params.dst.tile_x_sa;
params.y1 += params.dst.tile_y_sa;
}
}
params.num_samples = params.dst.surf.samples;
/* We may be restricted on the number of layers we can bind at any one
src/intel/blorp/blorp_genX_exec.h
+59 -4
View File
@@ -76,6 +76,10 @@ static void
blorp_emit_urb_config(struct blorp_batch *batch,
unsigned vs_entry_size, unsigned sf_entry_size);
static void
blorp_emit_pipeline(struct blorp_batch *batch,
const struct blorp_params *params);
/***** BEGIN blorp_exec implementation ******/
#include "genxml/gen_macros.h"
@@ -272,6 +276,9 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
vb[0].BufferAccessType = VERTEXDATA;
vb[0].EndAddress = vb[0].BufferStartingAddress;
vb[0].EndAddress.offset += size - 1;
#elif GEN_GEN == 4
vb[0].BufferAccessType = VERTEXDATA;
vb[0].MaxIndex = 2;
#endif
blorp_emit_input_varying_data(batch, params,
@@ -290,6 +297,9 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
vb[1].BufferAccessType = INSTANCEDATA;
vb[1].EndAddress = vb[1].BufferStartingAddress;
vb[1].EndAddress.offset += size - 1;
#elif GEN_GEN == 4
vb[1].BufferAccessType = INSTANCEDATA;
vb[1].MaxIndex = 0;
#endif
const unsigned num_dwords = 1 + GENX(VERTEX_BUFFER_STATE_length) * 2;
@@ -309,7 +319,8 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
{
const unsigned num_varyings =
params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0;
const unsigned num_elements = 2 + num_varyings;
bool need_ndc = batch->blorp->compiler->devinfo->gen <= 5;
const unsigned num_elements = 2 + need_ndc + num_varyings;
struct GENX(VERTEX_ELEMENT_STATE) ve[num_elements];
memset(ve, 0, num_elements * sizeof(*ve));
@@ -382,9 +393,32 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
#endif
.Component2Control = VFCOMP_STORE_SRC,
.Component3Control = VFCOMP_STORE_SRC,
#if GEN_GEN <= 5
.DestinationElementOffset = slot * 4,
#endif
};
slot++;
#if GEN_GEN <= 5
/* On Iron Lake and earlier, a native device coordinates version of the
* position goes right after the normal VUE header and before position.
* Since w == 1 for all of our coordinates, this is just a copy of the
* position.
*/
ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) {
.VertexBufferIndex = 0,
.Valid = true,
.SourceElementFormat = ISL_FORMAT_R32G32B32_FLOAT,
.SourceElementOffset = 0,
.Component0Control = VFCOMP_STORE_SRC,
.Component1Control = VFCOMP_STORE_SRC,
.Component2Control = VFCOMP_STORE_SRC,
.Component3Control = VFCOMP_STORE_1_FP,
.DestinationElementOffset = slot * 4,
};
slot++;
#endif
ve[slot] = (struct GENX(VERTEX_ELEMENT_STATE)) {
.VertexBufferIndex = 0,
.Valid = true,
@@ -394,6 +428,9 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
.Component1Control = VFCOMP_STORE_SRC,
.Component2Control = VFCOMP_STORE_SRC,
.Component3Control = VFCOMP_STORE_1_FP,
#if GEN_GEN <= 5
.DestinationElementOffset = slot * 4,
#endif
};
slot++;
@@ -407,6 +444,9 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
.Component1Control = VFCOMP_STORE_SRC,
.Component2Control = VFCOMP_STORE_SRC,
.Component3Control = VFCOMP_STORE_SRC,
#if GEN_GEN <= 5
.DestinationElementOffset = slot * 4,
#endif
};
slot++;
}
@@ -1162,6 +1202,7 @@ static void
blorp_emit_surface_state(struct blorp_batch *batch,
const struct brw_blorp_surface_info *surface,
void *state, uint32_t state_offset,
const bool color_write_disables[4],
bool is_render_target)
{
const struct isl_device *isl_dev = batch->blorp->isl_dev;
@@ -1178,13 +1219,26 @@ blorp_emit_surface_state(struct blorp_batch *batch,
if (aux_usage == ISL_AUX_USAGE_HIZ)
aux_usage = ISL_AUX_USAGE_NONE;
isl_channel_mask_t write_disable_mask = 0;
if (is_render_target && GEN_GEN <= 5) {
if (color_write_disables[0])
write_disable_mask |= ISL_CHANNEL_RED_BIT;
if (color_write_disables[1])
write_disable_mask |= ISL_CHANNEL_GREEN_BIT;
if (color_write_disables[2])
write_disable_mask |= ISL_CHANNEL_BLUE_BIT;
if (color_write_disables[3])
write_disable_mask |= ISL_CHANNEL_ALPHA_BIT;
}
const uint32_t mocs =
is_render_target ? batch->blorp->mocs.rb : batch->blorp->mocs.tex;
isl_surf_fill_state(batch->blorp->isl_dev, state,
.surf = &surf, .view = &surface->view,
.aux_surf = &surface->aux_surf, .aux_usage = aux_usage,
.mocs = mocs, .clear_color = surface->clear_color);
.mocs = mocs, .clear_color = surface->clear_color,
.write_disables = write_disable_mask);
blorp_surface_reloc(batch, state_offset + isl_dev->ss.addr_offset,
surface->addr, 0);
@@ -1257,7 +1311,7 @@ blorp_emit_surface_states(struct blorp_batch *batch,
blorp_emit_surface_state(batch, &params->dst,
surface_maps[BLORP_RENDERBUFFER_BT_INDEX],
surface_offsets[BLORP_RENDERBUFFER_BT_INDEX],
true);
params->color_write_disable, true);
} else {
assert(params->depth.enabled || params->stencil.enabled);
const struct brw_blorp_surface_info *surface =
@@ -1269,7 +1323,8 @@ blorp_emit_surface_states(struct blorp_batch *batch,
if (params->src.enabled) {
blorp_emit_surface_state(batch, &params->src,
surface_maps[BLORP_TEXTURE_BT_INDEX],
surface_offsets[BLORP_TEXTURE_BT_INDEX], false);
surface_offsets[BLORP_TEXTURE_BT_INDEX],
NULL, false);
}
}