From 74713469e1824e0e7caeb4ac05709ffb7b8ff98f Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 27 Jun 2024 12:07:36 +0200 Subject: [PATCH] radv: disable conditional rendering with DGC and task shaders When the DGC prepare shader is conditionally executed on the graphics queue, the generated IBs might be uninitialized. It's fine for the DGC GFX IB because the INDIRECT_PACKET would also be conditionally skipped but it's not possible to do that for the DGC ACE IB (ie. no IB2 on compute). Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_device_generated_commands.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device_generated_commands.c b/src/amd/vulkan/radv_device_generated_commands.c index 148984132cb..a6ad3a580f6 100644 --- a/src/amd/vulkan/radv_device_generated_commands.c +++ b/src/amd/vulkan/radv_device_generated_commands.c @@ -2295,9 +2295,12 @@ radv_use_dgc_predication(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCo /* Enable conditional rendering (if not enabled by user) to skip prepare/execute DGC calls when * the indirect sequence count might be zero. This can only be enabled on GFX because on ACE it's - * not possible to skip the execute DGC call (ie. no INDIRECT_PACKET) + * not possible to skip the execute DGC call (ie. no INDIRECT_PACKET). It should also be disabled + * when the graphics pipelines has a task shader for the same reason (otherwise the DGC ACE IB + * would be uninitialized). */ - return cmd_buffer->qf == RADV_QUEUE_GENERAL && seq_count_buffer && !cmd_buffer->state.predicating; + return cmd_buffer->qf == RADV_QUEUE_GENERAL && !radv_dgc_with_task_shader(pGeneratedCommandsInfo) && + seq_count_buffer && !cmd_buffer->state.predicating; } static bool