From 745ea994846b64a16a3368a87a74862910cf9b42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 17 Oct 2021 11:32:08 -0400 Subject: [PATCH] radeonsi: add SI_MAX_VRAM_MAP_SIZE definition Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_buffer.c | 7 ++----- src/gallium/drivers/radeonsi/si_pipe.h | 9 +++++++++ 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index a16c50a94f6..9977588132f 100644 --- a/src/gallium/drivers/radeonsi/si_buffer.c +++ b/src/gallium/drivers/radeonsi/si_buffer.c @@ -150,14 +150,11 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, if (res->domains & RADEON_DOMAIN_VRAM) { /* We don't want to evict buffers from VRAM by mapping them for CPU access, * because they might never be moved back again. If a buffer is large enough, - * upload data by copying from a temporary GTT buffer. 8K might not seem much, - * but there can be 100000 buffers. - * - * This tweak improves performance for viewperf creo & snx. + * upload data by copying from a temporary GTT buffer. */ if (!sscreen->info.smart_access_memory && sscreen->info.has_dedicated_vram && - size >= 8196) + size >= SI_MAX_VRAM_MAP_SIZE) res->b.b.flags |= PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY; } } diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 763af1a58d9..e297378578d 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -61,6 +61,15 @@ extern "C" { /* Alignment for optimal CP DMA performance. */ #define SI_CPDMA_ALIGNMENT 32 +/* We don't want to evict buffers from VRAM by mapping them for CPU access, + * because they might never be moved back again. If a buffer is large enough, + * upload data by copying from a temporary GTT buffer. 8K might not seem much, + * but there can be 100000 buffers. + * + * This tweak improves performance for viewperf creo & snx. + */ +#define SI_MAX_VRAM_MAP_SIZE 8196 + /* Tunables for compute-based clear_buffer and copy_buffer: */ #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4 #define SI_COMPUTE_COPY_DW_PER_THREAD 4