diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c
index 6efd4798503..a77a2167369 100644
--- a/src/asahi/compiler/agx_compile.c
+++ b/src/asahi/compiler/agx_compile.c
@@ -332,7 +332,7 @@ agx_emit_load_vary_flat(agx_builder *b, agx_index *dests, nir_intrinsic_instr *i
 
    for (unsigned i = 0; i < components; ++i) {
       /* vec3 for each vertex, unknown what first 2 channels are for */
-      agx_index values = agx_ld_vary_flat(b, cf, 1);
+      agx_index values = agx_ldcf(b, cf, 1);
       dests[i] = agx_p_extract(b, values, 2);
 
       /* Each component accesses a sequential coefficient register */
@@ -364,7 +364,7 @@ agx_emit_load_vary(agx_builder *b, agx_index *dests, nir_intrinsic_instr *instr)
                            components);
 
    agx_index vec = agx_vec_for_intr(b->shader, instr);
-   agx_ld_vary_to(b, vec, I, J, components, true);
+   agx_iter_to(b, vec, I, J, components, true);
    agx_emit_split(b, dests, vec, components);
 }
 
@@ -507,8 +507,8 @@ agx_emit_load_frag_coord(agx_builder *b, agx_index *dests, nir_intrinsic_instr *
    agx_index w = agx_get_cf(b->shader, true, false, VARYING_SLOT_POS, 3, 1);
    agx_index z = agx_get_cf(b->shader, true, false, VARYING_SLOT_POS, 2, 1);
 
-   dests[2] = agx_ld_vary(b, z, agx_null(), 1, false);
-   dests[3] = agx_ld_vary(b, w, agx_null(), 1, false);
+   dests[2] = agx_iter(b, z, agx_null(), 1, false);
+   dests[3] = agx_iter(b, w, agx_null(), 1, false);
 }
 
 static agx_instr *
diff --git a/src/asahi/compiler/agx_opcodes.py b/src/asahi/compiler/agx_opcodes.py
index 041366461e2..ab4bbecbc24 100644
--- a/src/asahi/compiler/agx_opcodes.py
+++ b/src/asahi/compiler/agx_opcodes.py
@@ -238,8 +238,8 @@ for is_float in [False, True]:
 
 op("bitop", (0x7E, 0x7F, 6, _), srcs = 2, imms = [TRUTH_TABLE])
 op("convert", (0x3E | L, 0x7F | L | (0x3 << 38), 6, _), srcs = 2, imms = [ROUND]) 
-op("ld_vary", (0x21, 0xBF, 8, _), srcs = 2, imms = [CHANNELS, PERSPECTIVE])
-op("ld_vary_flat", (0xA1, 0xBF, 8, _), srcs = 1, imms = [CHANNELS])
+op("iter", (0x21, 0xBF, 8, _), srcs = 2, imms = [CHANNELS, PERSPECTIVE])
+op("ldcf", (0xA1, 0xBF, 8, _), srcs = 1, imms = [CHANNELS])
 op("st_vary", None, dests = 0, srcs = 2, can_eliminate = False)
 op("stop", (0x88, 0xFFFF, 2, _), dests = 0, can_eliminate = False)
 op("trap", (0x08, 0xFFFF, 2, _), dests = 0, can_eliminate = False)
diff --git a/src/asahi/compiler/agx_pack.c b/src/asahi/compiler/agx_pack.c
index 1be77e5ca05..4baf1ee4160 100644
--- a/src/asahi/compiler/agx_pack.c
+++ b/src/asahi/compiler/agx_pack.c
@@ -446,10 +446,10 @@ agx_pack_instr(struct util_dynarray *emission, struct util_dynarray *fixups, agx
       break;
    }
 
-   case AGX_OPCODE_LD_VARY:
-   case AGX_OPCODE_LD_VARY_FLAT:
+   case AGX_OPCODE_ITER:
+   case AGX_OPCODE_LDCF:
    {
-      bool flat = (I->op == AGX_OPCODE_LD_VARY_FLAT);
+      bool flat = (I->op == AGX_OPCODE_LDCF);
       unsigned D = agx_pack_alu_dst(I->dest[0]);
       unsigned channels = (I->channels & 0x3);
       assert(I->mask < 0xF); /* 0 indicates full mask */
diff --git a/src/asahi/compiler/agx_register_allocate.c b/src/asahi/compiler/agx_register_allocate.c
index 05f38ce6059..d069cb66066 100644
--- a/src/asahi/compiler/agx_register_allocate.c
+++ b/src/asahi/compiler/agx_register_allocate.c
@@ -33,7 +33,7 @@ agx_write_registers(agx_instr *I, unsigned d)
    unsigned size = I->dest[d].size == AGX_SIZE_32 ? 2 : 1;
 
    switch (I->op) {
-   case AGX_OPCODE_LD_VARY:
+   case AGX_OPCODE_ITER:
       assert(1 <= I->channels && I->channels <= 4);
       return I->channels * size;
 
@@ -43,7 +43,7 @@ agx_write_registers(agx_instr *I, unsigned d)
       /* TODO: mask */
       return 4 * size;
 
-   case AGX_OPCODE_LD_VARY_FLAT:
+   case AGX_OPCODE_LDCF:
       return 6;
    case AGX_OPCODE_P_COMBINE:
    {