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radv,radeonsi: make TCS_OFFCHIP_LAYOUT_NUM_PATCHES not off by one

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We never use 128 anyway.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>
This commit is contained in:
Marek Olšák
2025-06-04 14:06:55 -04:00
committed by Marge Bot
parent 8d3e3c72e0
commit 742227c65c
7 changed files with 11 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/ac_shader_util.c
+2
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@@ -1022,6 +1022,8 @@ uint32_t ac_compute_num_tess_patches(const struct radeon_info *info, uint32_t nu
num_patches = MIN2(num_patches, one_wave);
}
/* This is the maximum number that fits into tcs_offchip_layout. */
assert(num_patches <= 127);
return num_patches;
}
src/amd/vulkan/nir/radv_nir_lower_abi.c
+2 -4
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@@ -80,8 +80,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
if (s->info->num_tess_patches) {
replacement = nir_imm_int(b, s->info->num_tess_patches);
} else {
nir_def *n = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
replacement = nir_iadd_imm_nuw(b, n, 1);
replacement = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
}
break;
case nir_intrinsic_load_tcs_tess_levels_to_tes_amd:
@@ -249,8 +248,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
if (s->info->num_tess_patches) {
num_patches = nir_imm_int(b, s->info->num_tess_patches);
} else {
nir_def *n = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
num_patches = nir_iadd_imm_nuw(b, n, 1);
num_patches = GET_SGPR_FIELD_NIR(s->args->tcs_offchip_layout, TCS_OFFCHIP_LAYOUT_NUM_PATCHES);
}
if (stage == MESA_SHADER_TESS_CTRL) {
src/amd/vulkan/radv_cmd_buffer.c
+1 -1
View File
@@ -10654,7 +10654,7 @@ radv_emit_tess_state(struct radv_cmd_buffer *cmd_buffer)
const uint32_t tcs_offchip_layout_offset = radv_get_user_sgpr_loc(tcs, AC_UD_TCS_OFFCHIP_LAYOUT);
const uint32_t tes_offchip_layout_offset = radv_get_user_sgpr_loc(tes, AC_UD_TCS_OFFCHIP_LAYOUT);
if (tcs_offchip_layout_offset) {
uint32_t tmp = SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_PATCHES, cmd_buffer->state.tess_num_patches - 1) |
uint32_t tmp = SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_PATCHES, cmd_buffer->state.tess_num_patches) |
SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_LS_OUTPUTS, vs->info.vs.num_linked_outputs) |
SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_NUM_HS_OUTPUTS, tcs->info.tcs.num_linked_outputs) |
SET_SGPR_FIELD(TCS_OFFCHIP_LAYOUT_TES_READS_TF, tes->info.tes.reads_tess_factors) |
src/amd/vulkan/radv_shader_args.h
+1 -1
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@@ -107,7 +107,7 @@ struct radv_shader_args {
struct ac_arg sample_mask;
/* TCS */
/* # [0:6] = the number of tessellation patches minus one, max = 127
/* # [0:6] = the number of tessellation patches, max = 127
* # [7:11] = TCS: the number of input patch control points minus one, max = 31
* TES: the number of output patch control points minus one, max = 31
* # [12:16] = (unused)