From 73e191924c09875f6118bb040343d87965fbba8e Mon Sep 17 00:00:00 2001 From: Faith Ekstrand Date: Wed, 31 May 2023 13:26:53 -0500 Subject: [PATCH] nir: Add a reg_intrinsics flag to nir_convert_from_ssa It doesn't do anything yet. We leave that to the subsequent patches so we can keep the tree-wide refactor as simple as possible. Reviewed-by: Alyssa Rosenzweig Part-of: --- src/broadcom/compiler/vir.c | 2 +- src/compiler/nir/nir.h | 7 +++++-- src/compiler/nir/nir_from_ssa.c | 4 +++- src/compiler/nir/tests/serialize_tests.cpp | 6 +++--- src/gallium/auxiliary/gallivm/lp_bld_nir.c | 2 +- src/gallium/auxiliary/nir/nir_to_tgsi.c | 2 +- src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c | 2 +- src/gallium/drivers/freedreno/a2xx/ir2_nir.c | 2 +- src/gallium/drivers/lima/lima_program.c | 4 ++-- src/gallium/drivers/r600/sfn/sfn_nir.cpp | 2 +- src/gallium/drivers/vc4/vc4_program.c | 2 +- src/gallium/drivers/zink/zink_compiler.c | 4 ++-- src/intel/compiler/brw_nir.c | 2 +- src/nouveau/codegen/nv50_ir_from_nir.cpp | 2 +- src/panfrost/midgard/midgard_compile.c | 2 +- 15 files changed, 25 insertions(+), 20 deletions(-) diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c index 82c21f9e326..660b11b0577 100644 --- a/src/broadcom/compiler/vir.c +++ b/src/broadcom/compiler/vir.c @@ -1624,7 +1624,7 @@ v3d_attempt_compile(struct v3d_compile *c) NIR_PASS(_, c->s, nir_lower_bool_to_int32); NIR_PASS(_, c->s, nir_convert_to_lcssa, true, true); NIR_PASS_V(c->s, nir_divergence_analysis); - NIR_PASS(_, c->s, nir_convert_from_ssa, true); + NIR_PASS(_, c->s, nir_convert_from_ssa, true, false); struct nir_schedule_options schedule_options = { /* Schedule for about half our register space, to enable more diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index e04b1d4aa24..1f3319467f2 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -5991,9 +5991,12 @@ bool nir_has_divergent_loop(nir_shader *shader); /* If phi_webs_only is true, only convert SSA values involved in phi nodes to * registers. If false, convert all values (even those not involved in a phi - * node) to registers. + * node) to registers. If reg_intrinsics is true, it will use + * decl/load/store_reg intrinsics instead of nir_register. */ -bool nir_convert_from_ssa(nir_shader *shader, bool phi_webs_only); +bool nir_convert_from_ssa(nir_shader *shader, + bool phi_webs_only, + bool reg_intrinsics); bool nir_lower_phis_to_regs_block(nir_block *block); bool nir_lower_ssa_defs_to_regs_block(nir_block *block); diff --git a/src/compiler/nir/nir_from_ssa.c b/src/compiler/nir/nir_from_ssa.c index 7b8454fbf4a..e53c7a1e115 100644 --- a/src/compiler/nir/nir_from_ssa.c +++ b/src/compiler/nir/nir_from_ssa.c @@ -906,7 +906,9 @@ nir_convert_from_ssa_impl(nir_function_impl *impl, bool phi_webs_only) } bool -nir_convert_from_ssa(nir_shader *shader, bool phi_webs_only) +nir_convert_from_ssa(nir_shader *shader, + bool phi_webs_only, + bool reg_intrinsics) { bool progress = false; diff --git a/src/compiler/nir/tests/serialize_tests.cpp b/src/compiler/nir/tests/serialize_tests.cpp index eeca83e4e73..c96752f12f3 100644 --- a/src/compiler/nir/tests/serialize_tests.cpp +++ b/src/compiler/nir/tests/serialize_tests.cpp @@ -194,7 +194,7 @@ TEST_P(nir_serialize_all_but_one_test, alu_two_components_reg_two_swizzle) memset(fma_alu->src[1].swizzle, 1, GetParam()); memset(fma_alu->src[2].swizzle, 1, GetParam()); - ASSERT_TRUE(nir_convert_from_ssa(b->shader, false)); + ASSERT_TRUE(nir_convert_from_ssa(b->shader, false, false)); fma_alu = get_last_alu(b->shader); ASSERT_FALSE(fma_alu->dest.dest.is_ssa); @@ -223,7 +223,7 @@ TEST_P(nir_serialize_all_but_one_test, alu_full_width_reg_two_swizzle) memset(fma_alu->src[1].swizzle, GetParam() - 1, GetParam()); memset(fma_alu->src[2].swizzle, GetParam() - 1, GetParam()); - ASSERT_TRUE(nir_convert_from_ssa(b->shader, false)); + ASSERT_TRUE(nir_convert_from_ssa(b->shader, false, false)); fma_alu = get_last_alu(b->shader); ASSERT_FALSE(fma_alu->dest.dest.is_ssa); @@ -251,7 +251,7 @@ TEST_P(nir_serialize_all_but_one_test, alu_two_component_reg_full_src) memset(fma_alu->src[1].swizzle, 1, GetParam()); memset(fma_alu->src[2].swizzle, 1, GetParam()); - ASSERT_TRUE(nir_convert_from_ssa(b->shader, false)); + ASSERT_TRUE(nir_convert_from_ssa(b->shader, false, false)); fma_alu = get_last_alu(b->shader); ASSERT_FALSE(fma_alu->dest.dest.is_ssa); diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.c b/src/gallium/auxiliary/gallivm/lp_bld_nir.c index 108907ca494..e27641087f2 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_nir.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.c @@ -2878,7 +2878,7 @@ bool lp_build_nir_llvm(struct lp_build_nir_context *bld_base, { struct nir_function *func; - NIR_PASS_V(nir, nir_convert_from_ssa, true); + NIR_PASS_V(nir, nir_convert_from_ssa, true, false); NIR_PASS_V(nir, nir_lower_locals_to_regs, 32); NIR_PASS_V(nir, nir_remove_dead_derefs); NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL); diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index 69cd95bbcfe..ba9b5f1a3e3 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -3867,7 +3867,7 @@ const void *nir_to_tgsi_options(struct nir_shader *s, source_mods |= nir_lower_fabs_source_mods; NIR_PASS_V(s, nir_lower_to_source_mods, source_mods); - NIR_PASS_V(s, nir_convert_from_ssa, true); + NIR_PASS_V(s, nir_convert_from_ssa, true, false); NIR_PASS_V(s, nir_lower_vec_to_movs, ntt_vec_to_mov_writemask_cb, NULL); /* locals_to_regs will leave dead derefs that are good to clean up. */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c index 2fae63076ca..29e538b0125 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c @@ -984,7 +984,7 @@ emit_shader(struct etna_compile *c, unsigned *num_temps, unsigned *num_consts) } /* call directly to avoid validation (load_const don't pass validation at this point) */ - nir_convert_from_ssa(shader, true); + nir_convert_from_ssa(shader, true, false); nir_opt_dce(shader); etna_ra_assign(c, shader); diff --git a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c index cfe12ab2fa1..400ef2fbd28 100644 --- a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c +++ b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c @@ -1119,7 +1119,7 @@ ir2_nir_compile(struct ir2_context *ctx, bool binning) OPT_V(ctx->nir, nir_lower_alu_to_scalar, ir2_alu_to_scalar_filter_cb, NULL); - OPT_V(ctx->nir, nir_convert_from_ssa, true); + OPT_V(ctx->nir, nir_convert_from_ssa, true, false); OPT_V(ctx->nir, nir_move_vec_src_uses_to_dest); OPT_V(ctx->nir, nir_lower_vec_to_movs, NULL, NULL); diff --git a/src/gallium/drivers/lima/lima_program.c b/src/gallium/drivers/lima/lima_program.c index 81dd63b1812..a7731610d92 100644 --- a/src/gallium/drivers/lima/lima_program.c +++ b/src/gallium/drivers/lima/lima_program.c @@ -152,7 +152,7 @@ lima_program_optimize_vs_nir(struct nir_shader *s) NIR_PASS_V(s, nir_copy_prop); NIR_PASS_V(s, nir_opt_dce); NIR_PASS_V(s, lima_nir_split_loads); - NIR_PASS_V(s, nir_convert_from_ssa, true); + NIR_PASS_V(s, nir_convert_from_ssa, true, false); NIR_PASS_V(s, nir_opt_dce); NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL); nir_sweep(s); @@ -270,7 +270,7 @@ lima_program_optimize_fs_nir(struct nir_shader *s, NIR_PASS_V(s, nir_copy_prop); NIR_PASS_V(s, nir_opt_dce); - NIR_PASS_V(s, nir_convert_from_ssa, true); + NIR_PASS_V(s, nir_convert_from_ssa, true, false); NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL); NIR_PASS_V(s, nir_move_vec_src_uses_to_dest); diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp index 3ecec29452c..2f54aaa5f88 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp @@ -936,7 +936,7 @@ r600_shader_from_nir(struct r600_context *rctx, NIR_PASS_V(sh, nir_lower_bool_to_int32); NIR_PASS_V(sh, nir_lower_locals_to_regs, 32); - NIR_PASS_V(sh, nir_convert_from_ssa, true); + NIR_PASS_V(sh, nir_convert_from_ssa, true, false); NIR_PASS_V(sh, nir_opt_dce); if (rctx->screen->b.debug_flags & DBG_ALL_SHADERS) { diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index 4bc8b9195e5..0639485c607 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -2333,7 +2333,7 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage, NIR_PASS_V(c->s, nir_lower_bool_to_int32); - NIR_PASS_V(c->s, nir_convert_from_ssa, true); + NIR_PASS_V(c->s, nir_convert_from_ssa, true, false); if (VC4_DBG(NIR)) { fprintf(stderr, "%s prog %d/%d NIR:\n", diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c index cdb1bb84a7a..34303034b76 100644 --- a/src/gallium/drivers/zink/zink_compiler.c +++ b/src/gallium/drivers/zink/zink_compiler.c @@ -3493,7 +3493,7 @@ compile_module(struct zink_screen *screen, struct zink_shader *zs, nir_shader *n struct zink_shader_info *sinfo = &zs->sinfo; prune_io(nir); - NIR_PASS_V(nir, nir_convert_from_ssa, true); + NIR_PASS_V(nir, nir_convert_from_ssa, true, false); struct zink_shader_object obj; struct spirv_shader *spirv = nir_to_spirv(nir, sinfo, screen->spirv_version); @@ -5275,7 +5275,7 @@ zink_shader_tcs_create(struct zink_screen *screen, nir_shader *tes, unsigned ver optimize_nir(nir, NULL); NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_function_temp, NULL); - NIR_PASS_V(nir, nir_convert_from_ssa, true); + NIR_PASS_V(nir, nir_convert_from_ssa, true, false); *nir_ret = nir; zink_shader_serialize_blob(nir, &ret->blob); diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 4f82fa042d8..415502e4cb1 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1722,7 +1722,7 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler, nir_validate_ssa_dominance(nir, "before nir_convert_from_ssa"); - OPT(nir_convert_from_ssa, true); + OPT(nir_convert_from_ssa, true, false); if (!is_scalar) { OPT(nir_move_vec_src_uses_to_dest); diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp index 58f633cf3ef..d170a1e6fff 100644 --- a/src/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp @@ -3257,7 +3257,7 @@ Converter::run() NIR_PASS_V(nir, nir_lower_bool_to_int32); NIR_PASS_V(nir, nir_lower_bit_size, Converter::lowerBitSizeCB, this); - NIR_PASS_V(nir, nir_convert_from_ssa, true); + NIR_PASS_V(nir, nir_convert_from_ssa, true, false); // Garbage collect dead instructions nir_sweep(nir); diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index d1ba982a376..13bfb75b0d4 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -480,7 +480,7 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend) NIR_PASS_V(nir, nir_opt_move, move_all); /* Take us out of SSA */ - NIR_PASS(progress, nir, nir_convert_from_ssa, true); + NIR_PASS(progress, nir, nir_convert_from_ssa, true, false); /* We are a vector architecture; write combine where possible */ NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);