intel/compiler: Use FS thread payload only for FS
Move the setup into the FS thread payload constructor. Consolidate payload setup for that in brw_fs_thread_payload.cpp file. Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18176>
This commit is contained in:
Caio Oliveira
@@ -0,0 +1,264 @@
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/*
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* Copyright © 2006-2022 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_fs.h"
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using namespace brw;
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static inline void
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setup_fs_payload_gfx6(fs_thread_payload &payload,
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const fs_visitor &v,
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bool &source_depth_to_render_target)
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{
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struct brw_wm_prog_data *prog_data = brw_wm_prog_data(v.prog_data);
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const unsigned payload_width = MIN2(16, v.dispatch_width);
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assert(v.dispatch_width % payload_width == 0);
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assert(v.devinfo->ver >= 6);
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payload.num_regs = 0;
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/* R0: PS thread payload header. */
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payload.num_regs++;
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for (unsigned j = 0; j < v.dispatch_width / payload_width; j++) {
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/* R1: masks, pixel X/Y coordinates. */
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payload.subspan_coord_reg[j] = payload.num_regs++;
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}
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for (unsigned j = 0; j < v.dispatch_width / payload_width; j++) {
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/* R3-26: barycentric interpolation coordinates. These appear in the
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* same order that they appear in the brw_barycentric_mode enum. Each
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* set of coordinates occupies 2 registers if dispatch width == 8 and 4
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* registers if dispatch width == 16. Coordinates only appear if they
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* were enabled using the "Barycentric Interpolation Mode" bits in
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* WM_STATE.
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*/
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for (int i = 0; i < BRW_BARYCENTRIC_MODE_COUNT; ++i) {
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if (prog_data->barycentric_interp_modes & (1 << i)) {
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payload.barycentric_coord_reg[i][j] = payload.num_regs;
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payload.num_regs += payload_width / 4;
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}
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}
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/* R27-28: interpolated depth if uses source depth */
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if (prog_data->uses_src_depth) {
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payload.source_depth_reg[j] = payload.num_regs;
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payload.num_regs += payload_width / 8;
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}
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/* R29-30: interpolated W set if GFX6_WM_USES_SOURCE_W. */
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if (prog_data->uses_src_w) {
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payload.source_w_reg[j] = payload.num_regs;
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payload.num_regs += payload_width / 8;
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}
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/* R31: MSAA position offsets. */
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if (prog_data->uses_pos_offset) {
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payload.sample_pos_reg[j] = payload.num_regs;
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payload.num_regs++;
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}
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/* R32-33: MSAA input coverage mask */
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if (prog_data->uses_sample_mask) {
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assert(v.devinfo->ver >= 7);
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payload.sample_mask_in_reg[j] = payload.num_regs;
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payload.num_regs += payload_width / 8;
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}
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/* R66: Source Depth and/or W Attribute Vertex Deltas */
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if (prog_data->uses_depth_w_coefficients) {
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payload.depth_w_coef_reg[j] = payload.num_regs;
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payload.num_regs++;
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}
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}
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if (v.nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
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source_depth_to_render_target = true;
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}
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}
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#undef P /* prompted depth */
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#undef C /* computed */
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#undef N /* non-promoted? */
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#define P 0
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#define C 1
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#define N 2
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static const struct {
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GLuint mode:2;
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GLuint sd_present:1;
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GLuint sd_to_rt:1;
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GLuint dd_present:1;
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GLuint ds_present:1;
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} wm_iz_table[BRW_WM_IZ_BIT_MAX] =
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{
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 0 },
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{ N, 0, 1, 0, 0 },
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{ N, 0, 1, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 1, 1, 0 },
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{ C, 0, 1, 1, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 0 },
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{ C, 0, 1, 1, 0 },
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{ C, 0, 1, 1, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 0 },
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{ N, 0, 1, 0, 0 },
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{ N, 0, 1, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 1, 1, 0 },
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{ C, 0, 1, 1, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 0 },
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{ C, 0, 1, 1, 0 },
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{ C, 0, 1, 1, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 1 },
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{ N, 0, 1, 0, 1 },
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{ N, 0, 1, 0, 1 },
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{ P, 0, 0, 0, 0 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ P, 0, 0, 0, 0 },
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{ N, 1, 1, 0, 1 },
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{ C, 0, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 0, 0, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 0, 1, 0, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 1, 1, 0, 1 },
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{ C, 0, 1, 0, 1 },
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{ C, 0, 1, 0, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 1, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ P, 0, 0, 0, 0 },
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{ C, 1, 1, 1, 1 },
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{ C, 0, 1, 1, 1 },
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{ C, 0, 1, 1, 1 }
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};
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/**
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* \param line_aa BRW_WM_AA_NEVER, BRW_WM_AA_ALWAYS or BRW_WM_AA_SOMETIMES
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* \param lookup bitmask of BRW_WM_IZ_* flags
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*/
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static inline void
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setup_fs_payload_gfx4(fs_thread_payload &payload,
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const fs_visitor &v,
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bool &source_depth_to_render_target,
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bool &runtime_check_aads_emit)
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{
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assert(v.dispatch_width <= 16);
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struct brw_wm_prog_data *prog_data = brw_wm_prog_data(v.prog_data);
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brw_wm_prog_key *key = (brw_wm_prog_key *) v.key;
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GLuint reg = 1;
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bool kill_stats_promoted_workaround = false;
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int lookup = key->iz_lookup;
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assert(lookup < BRW_WM_IZ_BIT_MAX);
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/* Crazy workaround in the windowizer, which we need to track in
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* our register allocation and render target writes. See the "If
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* statistics are enabled..." paragraph of 11.5.3.2: Early Depth
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* Test Cases [Pre-DevGT] of the 3D Pipeline - Windower B-Spec.
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*/
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if (key->stats_wm &&
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(lookup & BRW_WM_IZ_PS_KILL_ALPHATEST_BIT) &&
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wm_iz_table[lookup].mode == P) {
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kill_stats_promoted_workaround = true;
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}
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payload.subspan_coord_reg[0] = reg++;
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if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
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kill_stats_promoted_workaround) {
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payload.source_depth_reg[0] = reg;
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reg += 2;
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}
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if (wm_iz_table[lookup].sd_to_rt || kill_stats_promoted_workaround)
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source_depth_to_render_target = true;
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if (wm_iz_table[lookup].ds_present || key->line_aa != BRW_WM_AA_NEVER) {
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payload.aa_dest_stencil_reg[0] = reg;
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runtime_check_aads_emit =
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!wm_iz_table[lookup].ds_present && key->line_aa == BRW_WM_AA_SOMETIMES;
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reg++;
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}
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if (wm_iz_table[lookup].dd_present) {
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payload.dest_depth_reg[0] = reg;
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reg+=2;
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}
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payload.num_regs = reg;
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}
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#undef P /* prompted depth */
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#undef C /* computed */
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#undef N /* non-promoted? */
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fs_thread_payload::fs_thread_payload(const fs_visitor &v,
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bool &source_depth_to_render_target,
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bool &runtime_check_aads_emit)
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: subspan_coord_reg(),
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source_depth_reg(),
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source_w_reg(),
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aa_dest_stencil_reg(),
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dest_depth_reg(),
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sample_pos_reg(),
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sample_mask_in_reg(),
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depth_w_coef_reg(),
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barycentric_coord_reg(),
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local_invocation_id_reg()
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{
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if (v.devinfo->ver >= 6)
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setup_fs_payload_gfx6(*this, v, source_depth_to_render_target);
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else
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setup_fs_payload_gfx4(*this, v, source_depth_to_render_target,
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runtime_check_aads_emit);
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}
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