diff --git a/src/gallium/drivers/crocus/crocus_batch.c b/src/gallium/drivers/crocus/crocus_batch.c
index 8073f7813d0..8a1f4cbf8e4 100644
--- a/src/gallium/drivers/crocus/crocus_batch.c
+++ b/src/gallium/drivers/crocus/crocus_batch.c
@@ -254,7 +254,8 @@ crocus_init_batch(struct crocus_context *ice,
          (INTEL_DEBUG(DEBUG_COLOR) ? INTEL_BATCH_DECODE_IN_COLOR : 0) |
          INTEL_BATCH_DECODE_OFFSETS | INTEL_BATCH_DECODE_FLOATS;
 
-      intel_batch_decode_ctx_init(&batch->decoder, &screen->devinfo, stderr,
+      intel_batch_decode_ctx_init(&batch->decoder, &screen->compiler->isa,
+                                  &screen->devinfo, stderr,
                                   decode_flags, NULL, decode_get_bo,
                                   decode_get_state_size, batch);
       batch->decoder.max_vbo_decoded_lines = 32;
diff --git a/src/gallium/drivers/crocus/crocus_program_cache.c b/src/gallium/drivers/crocus/crocus_program_cache.c
index 11c3e400290..a55e469482f 100644
--- a/src/gallium/drivers/crocus/crocus_program_cache.c
+++ b/src/gallium/drivers/crocus/crocus_program_cache.c
@@ -334,13 +334,13 @@ void
 crocus_print_program_cache(struct crocus_context *ice)
 {
    struct crocus_screen *screen = (struct crocus_screen *)ice->ctx.screen;
-   const struct intel_device_info *devinfo = &screen->devinfo;
+   const struct brw_isa_info *isa = &screen->compiler->isa;
 
    hash_table_foreach(ice->shaders.cache, entry) {
       const struct keybox *keybox = entry->key;
       struct crocus_compiled_shader *shader = entry->data;
       fprintf(stderr, "%s:\n", cache_name(keybox->cache_id));
-      brw_disassemble(devinfo, ice->shaders.cache_bo_map + shader->offset, 0,
+      brw_disassemble(isa, ice->shaders.cache_bo_map + shader->offset, 0,
                       shader->prog_data->program_size, NULL, stderr);
    }
 }
diff --git a/src/gallium/drivers/iris/iris_batch.c b/src/gallium/drivers/iris/iris_batch.c
index 9886497ca25..6170fe94fef 100644
--- a/src/gallium/drivers/iris/iris_batch.c
+++ b/src/gallium/drivers/iris/iris_batch.c
@@ -230,7 +230,8 @@ iris_init_batch(struct iris_context *ice,
          INTEL_BATCH_DECODE_OFFSETS |
          INTEL_BATCH_DECODE_FLOATS;
 
-      intel_batch_decode_ctx_init(&batch->decoder, &screen->devinfo,
+      intel_batch_decode_ctx_init(&batch->decoder, &screen->compiler->isa,
+                                  &screen->devinfo,
                                   stderr, decode_flags, NULL,
                                   decode_get_bo, decode_get_state_size, batch);
       batch->decoder.dynamic_base = IRIS_MEMZONE_DYNAMIC_START;
diff --git a/src/gallium/drivers/iris/iris_program_cache.c b/src/gallium/drivers/iris/iris_program_cache.c
index f9db5a526a4..a523c5bb2f2 100644
--- a/src/gallium/drivers/iris/iris_program_cache.c
+++ b/src/gallium/drivers/iris/iris_program_cache.c
@@ -179,7 +179,7 @@ iris_upload_shader(struct iris_screen *screen,
          .value = shader_data_addr >> 32,
       },
    };
-   brw_write_shader_relocs(&screen->devinfo, shader->map,
+   brw_write_shader_relocs(&screen->compiler->isa, shader->map,
                            shader->prog_data, reloc_values,
                            ARRAY_SIZE(reloc_values));
 
diff --git a/src/intel/common/intel_batch_decoder.c b/src/intel/common/intel_batch_decoder.c
index 20f4a8f1c24..a73afdf1fc6 100644
--- a/src/intel/common/intel_batch_decoder.c
+++ b/src/intel/common/intel_batch_decoder.c
@@ -30,6 +30,7 @@
 
 void
 intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
+                            const struct brw_isa_info *isa,
                             const struct intel_device_info *devinfo,
                             FILE *fp, enum intel_batch_decode_flags flags,
                             const char *xml_path,
@@ -42,6 +43,7 @@ intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
 {
    memset(ctx, 0, sizeof(*ctx));
 
+   ctx->isa = isa;
    ctx->devinfo = *devinfo;
    ctx->get_bo = get_bo;
    ctx->get_state_size = get_state_size;
@@ -137,7 +139,7 @@ ctx_disassemble_program(struct intel_batch_decode_ctx *ctx,
       return;
 
    fprintf(ctx->fp, "\nReferenced %s:\n", type);
-   intel_disassemble(&ctx->devinfo, bo.map, 0, ctx->fp);
+   intel_disassemble(ctx->isa, bo.map, 0, ctx->fp);
 }
 
 /* Heuristic to determine whether a uint32_t is probably actually a float
diff --git a/src/intel/common/intel_batch_decoder_stub.c b/src/intel/common/intel_batch_decoder_stub.c
index eb19df98dae..27bfeb42946 100644
--- a/src/intel/common/intel_batch_decoder_stub.c
+++ b/src/intel/common/intel_batch_decoder_stub.c
@@ -26,6 +26,7 @@
 
 void
 intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
+                            const struct brw_isa_info *isa,
                             const struct intel_device_info *devinfo,
                             FILE *fp, enum intel_batch_decode_flags flags,
                             const char *xml_path,
diff --git a/src/intel/common/intel_decoder.h b/src/intel/common/intel_decoder.h
index 3a2b692dc49..7a48826ef6b 100644
--- a/src/intel/common/intel_decoder.h
+++ b/src/intel/common/intel_decoder.h
@@ -238,6 +238,7 @@ struct intel_batch_decode_ctx {
    void *user_data;
 
    FILE *fp;
+   const struct brw_isa_info *isa;
    struct intel_device_info devinfo;
    struct intel_spec *spec;
    enum intel_batch_decode_flags flags;
@@ -257,6 +258,7 @@ struct intel_batch_decode_ctx {
 };
 
 void intel_batch_decode_ctx_init(struct intel_batch_decode_ctx *ctx,
+                                 const struct brw_isa_info *isa,
                                  const struct intel_device_info *devinfo,
                                  FILE *fp, enum intel_batch_decode_flags flags,
                                  const char *xml_path,
diff --git a/src/intel/common/intel_disasm.c b/src/intel/common/intel_disasm.c
index 90d5a9935ce..354676ccadf 100644
--- a/src/intel/common/intel_disasm.c
+++ b/src/intel/common/intel_disasm.c
@@ -25,6 +25,7 @@
 
 #include "compiler/brw_inst.h"
 #include "compiler/brw_eu.h"
+#include "compiler/brw_isa_info.h"
 
 #include "intel_disasm.h"
 
@@ -38,9 +39,10 @@ is_send(uint32_t opcode)
 }
 
 static int
-intel_disasm_find_end(const struct intel_device_info *devinfo,
+intel_disasm_find_end(const struct brw_isa_info *isa,
                       const void *assembly, int start)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
    int offset = start;
 
    /* This loop exits when send-with-EOT or when opcode is 0 */
@@ -54,7 +56,7 @@ intel_disasm_find_end(const struct intel_device_info *devinfo,
       }
 
       /* Simplistic, but efficient way to terminate disasm */
-      uint32_t opcode = brw_inst_opcode(devinfo, insn);
+      uint32_t opcode = brw_inst_opcode(isa, insn);
       if (opcode == 0 || (is_send(opcode) && brw_inst_eot(devinfo, insn))) {
          break;
       }
@@ -64,23 +66,23 @@ intel_disasm_find_end(const struct intel_device_info *devinfo,
 }
 
 void
-intel_disassemble(const struct intel_device_info *devinfo,
+intel_disassemble(const struct brw_isa_info *isa,
                   const void *assembly, int start, FILE *out)
 {
-   int end = intel_disasm_find_end(devinfo, assembly, start);
+   int end = intel_disasm_find_end(isa, assembly, start);
 
    /* Make a dummy disasm structure that brw_validate_instructions
     * can work from.
     */
-   struct disasm_info *disasm_info = disasm_initialize(devinfo, NULL);
+   struct disasm_info *disasm_info = disasm_initialize(isa, NULL);
    disasm_new_inst_group(disasm_info, start);
    disasm_new_inst_group(disasm_info, end);
 
-   brw_validate_instructions(devinfo, assembly, start, end, disasm_info);
+   brw_validate_instructions(isa, assembly, start, end, disasm_info);
 
    void *mem_ctx = ralloc_context(NULL);
    const struct brw_label *root_label =
-      brw_label_assembly(devinfo, assembly, start, end, mem_ctx);
+      brw_label_assembly(isa, assembly, start, end, mem_ctx);
 
    foreach_list_typed(struct inst_group, group, link,
                       &disasm_info->group_list) {
@@ -94,7 +96,7 @@ intel_disassemble(const struct intel_device_info *devinfo,
       int start_offset = group->offset;
       int end_offset = next->offset;
 
-      brw_disassemble(devinfo, assembly, start_offset, end_offset,
+      brw_disassemble(isa, assembly, start_offset, end_offset,
                       root_label, out);
 
       if (group->error) {
diff --git a/src/intel/common/intel_disasm.h b/src/intel/common/intel_disasm.h
index bb44bf6ec89..4d4fd1bcc8f 100644
--- a/src/intel/common/intel_disasm.h
+++ b/src/intel/common/intel_disasm.h
@@ -25,12 +25,13 @@
 #define INTEL_DISASM_H
 
 #include "intel/dev/intel_device_info.h"
+#include "compiler/brw_isa_info.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-void intel_disassemble(const struct intel_device_info *devinfo,
+void intel_disassemble(const struct brw_isa_info *isa,
                        const void *assembly, int start, FILE *out);
 
 #ifdef __cplusplus
diff --git a/src/intel/compiler/brw_compile_clip.c b/src/intel/compiler/brw_compile_clip.c
index d116c927d5f..60422389218 100644
--- a/src/intel/compiler/brw_compile_clip.c
+++ b/src/intel/compiler/brw_compile_clip.c
@@ -38,7 +38,7 @@ brw_compile_clip(const struct brw_compiler *compiler,
 
    /* Begin the compilation:
     */
-   brw_init_codegen(compiler->devinfo, &c.func, mem_ctx);
+   brw_init_codegen(&compiler->isa, &c.func, mem_ctx);
 
    c.func.single_program_flow = 1;
 
@@ -87,7 +87,7 @@ brw_compile_clip(const struct brw_compiler *compiler,
 
    if (INTEL_DEBUG(DEBUG_CLIP)) {
       fprintf(stderr, "clip:\n");
-      brw_disassemble_with_labels(compiler->devinfo,
+      brw_disassemble_with_labels(&compiler->isa,
                                   program, 0, *final_assembly_size, stderr);
       fprintf(stderr, "\n");
    }
diff --git a/src/intel/compiler/brw_compile_ff_gs.c b/src/intel/compiler/brw_compile_ff_gs.c
index edadac08091..57c63f35576 100644
--- a/src/intel/compiler/brw_compile_ff_gs.c
+++ b/src/intel/compiler/brw_compile_ff_gs.c
@@ -580,7 +580,7 @@ brw_compile_ff_gs_prog(struct brw_compiler *compiler,
 
    /* Begin the compilation:
     */
-   brw_init_codegen(compiler->devinfo, &c.func, mem_ctx);
+   brw_init_codegen(&compiler->isa, &c.func, mem_ctx);
 
    c.func.single_program_flow = 1;
 
@@ -651,7 +651,7 @@ brw_compile_ff_gs_prog(struct brw_compiler *compiler,
 
    if (INTEL_DEBUG(DEBUG_GS)) {
       fprintf(stderr, "gs:\n");
-      brw_disassemble_with_labels(compiler->devinfo, c.func.store,
+      brw_disassemble_with_labels(&compiler->isa, c.func.store,
                                   0, *final_assembly_size, stderr);
       fprintf(stderr, "\n");
     }
diff --git a/src/intel/compiler/brw_compile_sf.c b/src/intel/compiler/brw_compile_sf.c
index bbd2aec47a9..94f95aaaf3a 100644
--- a/src/intel/compiler/brw_compile_sf.c
+++ b/src/intel/compiler/brw_compile_sf.c
@@ -813,7 +813,7 @@ brw_compile_sf(const struct brw_compiler *compiler,
 
    /* Begin the compilation:
     */
-   brw_init_codegen(compiler->devinfo, &c.func, mem_ctx);
+   brw_init_codegen(&compiler->isa, &c.func, mem_ctx);
 
    c.key = *key;
    c.vue_map = *vue_map;
@@ -871,7 +871,7 @@ brw_compile_sf(const struct brw_compiler *compiler,
 
    if (INTEL_DEBUG(DEBUG_SF)) {
       fprintf(stderr, "sf:\n");
-      brw_disassemble_with_labels(compiler->devinfo,
+      brw_disassemble_with_labels(&compiler->isa,
                                   program, 0, *final_assembly_size, stderr);
       fprintf(stderr, "\n");
    }
diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index 601e60ed37b..5c9e022d21c 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -107,6 +107,8 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
 
    compiler->devinfo = devinfo;
 
+   brw_init_isa_info(&compiler->isa, devinfo);
+
    brw_fs_alloc_reg_sets(compiler);
    brw_vec4_alloc_reg_set(compiler);
 
@@ -278,7 +280,7 @@ brw_prog_key_size(gl_shader_stage stage)
 }
 
 void
-brw_write_shader_relocs(const struct intel_device_info *devinfo,
+brw_write_shader_relocs(const struct brw_isa_info *isa,
                         void *program,
                         const struct brw_stage_prog_data *prog_data,
                         struct brw_shader_reloc_value *values,
@@ -295,7 +297,7 @@ brw_write_shader_relocs(const struct intel_device_info *devinfo,
                *(uint32_t *)dst = value;
                break;
             case BRW_SHADER_RELOC_TYPE_MOV_IMM:
-               brw_update_reloc_imm(devinfo, dst, value);
+               brw_update_reloc_imm(isa, dst, value);
                break;
             default:
                unreachable("Invalid relocation type");
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index aa2e062a18e..8fc90815df7 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -29,6 +29,7 @@
 #include "dev/intel_device_info.h"
 #include "util/ralloc.h"
 #include "util/u_math.h"
+#include "brw_isa_info.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -50,6 +51,8 @@ struct brw_compiler {
     */
    mtx_t mutex;
 
+   struct brw_isa_info isa;
+
    struct {
       struct ra_regs *regs;
 
@@ -1910,7 +1913,7 @@ brw_cs_push_const_total_size(const struct brw_cs_prog_data *cs_prog_data,
                              unsigned threads);
 
 void
-brw_write_shader_relocs(const struct intel_device_info *devinfo,
+brw_write_shader_relocs(const struct brw_isa_info *isa,
                         void *program,
                         const struct brw_stage_prog_data *prog_data,
                         struct brw_shader_reloc_value *values,
diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index f87a842e08f..4228e5d8377 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -816,10 +816,10 @@ control(FILE *file, const char *name, const char *const ctrl[],
 }
 
 static int
-print_opcode(FILE *file, const struct intel_device_info *devinfo,
+print_opcode(FILE *file, const struct brw_isa_info *isa,
              enum opcode id)
 {
-   const struct opcode_desc *desc = brw_opcode_desc(devinfo, id);
+   const struct opcode_desc *desc = brw_opcode_desc(isa, id);
    if (!desc) {
       format(file, "*** invalid opcode value %d ", id);
       return 1;
@@ -891,13 +891,14 @@ reg(FILE *file, unsigned _reg_file, unsigned _reg_nr)
 }
 
 static int
-dest(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
+dest(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
    enum brw_reg_type type = brw_inst_dst_type(devinfo, inst);
    unsigned elem_size = brw_reg_type_to_size(type);
    int err = 0;
 
-   if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
+   if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) {
       /* These are fixed for split sends */
       type = BRW_REGISTER_TYPE_UD;
       elem_size = 4;
@@ -1493,9 +1494,11 @@ src2_3src(FILE *file, const struct intel_device_info *devinfo,
 }
 
 static int
-imm(FILE *file, const struct intel_device_info *devinfo, enum brw_reg_type type,
+imm(FILE *file, const struct brw_isa_info *isa, enum brw_reg_type type,
     const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    switch (type) {
    case BRW_REGISTER_TYPE_UQ:
       format(file, "0x%016"PRIx64"UQ", brw_inst_imm_uq(devinfo, inst));
@@ -1534,7 +1537,7 @@ imm(FILE *file, const struct intel_device_info *devinfo, enum brw_reg_type type,
       /* The DIM instruction's src0 uses an F type but contains a
        * 64-bit immediate
        */
-      if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM) {
+      if (brw_inst_opcode(isa, inst) == BRW_OPCODE_DIM) {
          format(file, "0x%"PRIx64"F", brw_inst_bits(inst, 127, 64));
          pad(file, 48);
          format(file, "/* %-gF */", brw_inst_imm_df(devinfo, inst));
@@ -1612,9 +1615,11 @@ src_send_desc_ia(FILE *file,
 }
 
 static int
-src0(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
+src0(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
 {
-   if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
+   if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) {
       if (devinfo->ver >= 12) {
          return src_sends_da(file,
                              devinfo,
@@ -1637,12 +1642,12 @@ src0(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
                              brw_inst_src0_ia_subreg_nr(devinfo, inst));
       }
    } else if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
-      return imm(file, devinfo, brw_inst_src0_type(devinfo, inst), inst);
+      return imm(file, isa, brw_inst_src0_type(devinfo, inst), inst);
    } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
       if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
          return src_da1(file,
                         devinfo,
-                        brw_inst_opcode(devinfo, inst),
+                        brw_inst_opcode(isa, inst),
                         brw_inst_src0_type(devinfo, inst),
                         brw_inst_src0_reg_file(devinfo, inst),
                         brw_inst_src0_vstride(devinfo, inst),
@@ -1655,7 +1660,7 @@ src0(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
       } else {
          return src_ia1(file,
                         devinfo,
-                        brw_inst_opcode(devinfo, inst),
+                        brw_inst_opcode(isa, inst),
                         brw_inst_src0_type(devinfo, inst),
                         brw_inst_src0_ia1_addr_imm(devinfo, inst),
                         brw_inst_src0_ia_subreg_nr(devinfo, inst),
@@ -1669,7 +1674,7 @@ src0(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
       if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
          return src_da16(file,
                          devinfo,
-                         brw_inst_opcode(devinfo, inst),
+                         brw_inst_opcode(isa, inst),
                          brw_inst_src0_type(devinfo, inst),
                          brw_inst_src0_reg_file(devinfo, inst),
                          brw_inst_src0_vstride(devinfo, inst),
@@ -1689,9 +1694,11 @@ src0(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
 }
 
 static int
-src1(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
+src1(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
 {
-   if (is_split_send(devinfo, brw_inst_opcode(devinfo, inst))) {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
+   if (is_split_send(devinfo, brw_inst_opcode(isa, inst))) {
       return src_sends_da(file,
                           devinfo,
                           BRW_REGISTER_TYPE_UD,
@@ -1699,12 +1706,12 @@ src1(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
                           brw_inst_send_src1_reg_nr(devinfo, inst),
                           0 /* subreg_nr */);
    } else if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
-      return imm(file, devinfo, brw_inst_src1_type(devinfo, inst), inst);
+      return imm(file, isa, brw_inst_src1_type(devinfo, inst), inst);
    } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
       if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
          return src_da1(file,
                         devinfo,
-                        brw_inst_opcode(devinfo, inst),
+                        brw_inst_opcode(isa, inst),
                         brw_inst_src1_type(devinfo, inst),
                         brw_inst_src1_reg_file(devinfo, inst),
                         brw_inst_src1_vstride(devinfo, inst),
@@ -1717,7 +1724,7 @@ src1(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
       } else {
          return src_ia1(file,
                         devinfo,
-                        brw_inst_opcode(devinfo, inst),
+                        brw_inst_opcode(isa, inst),
                         brw_inst_src1_type(devinfo, inst),
                         brw_inst_src1_ia1_addr_imm(devinfo, inst),
                         brw_inst_src1_ia_subreg_nr(devinfo, inst),
@@ -1731,7 +1738,7 @@ src1(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
       if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
          return src_da16(file,
                          devinfo,
-                         brw_inst_opcode(devinfo, inst),
+                         brw_inst_opcode(isa, inst),
                          brw_inst_src1_type(devinfo, inst),
                          brw_inst_src1_reg_file(devinfo, inst),
                          brw_inst_src1_vstride(devinfo, inst),
@@ -1786,9 +1793,10 @@ qtr_ctrl(FILE *file, const struct intel_device_info *devinfo,
 }
 
 static int
-swsb(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
+swsb(FILE *file, const struct brw_isa_info *isa, const brw_inst *inst)
 {
-   const enum opcode opcode = brw_inst_opcode(devinfo, inst);
+   const struct intel_device_info *devinfo = isa->devinfo;
+   const enum opcode opcode = brw_inst_opcode(isa, inst);
    const uint8_t x = brw_inst_swsb(devinfo, inst);
    const struct tgl_swsb swsb = tgl_swsb_decode(devinfo, opcode, x);
    if (swsb.regdist)
@@ -1807,13 +1815,13 @@ swsb(FILE *file, const struct intel_device_info *devinfo, const brw_inst *inst)
 
 #ifdef DEBUG
 static __attribute__((__unused__)) int
-brw_disassemble_imm(const struct intel_device_info *devinfo,
+brw_disassemble_imm(const struct brw_isa_info *isa,
                     uint32_t dw3, uint32_t dw2, uint32_t dw1, uint32_t dw0)
 {
    brw_inst inst;
    inst.data[0] = (((uint64_t) dw1) << 32) | ((uint64_t) dw0);
    inst.data[1] = (((uint64_t) dw3) << 32) | ((uint64_t) dw2);
-   return brw_disassemble_inst(stderr, devinfo, &inst, false, 0, NULL);
+   return brw_disassemble_inst(stderr, isa, &inst, false, 0, NULL);
 }
 #endif
 
@@ -1877,15 +1885,17 @@ brw_sfid_is_lsc(unsigned sfid)
 }
 
 int
-brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
+brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
                      const brw_inst *inst, bool is_compacted,
                      int offset, const struct brw_label *root_label)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    int err = 0;
    int space = 0;
 
-   const enum opcode opcode = brw_inst_opcode(devinfo, inst);
-   const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
+   const enum opcode opcode = brw_inst_opcode(isa, inst);
+   const struct opcode_desc *desc = brw_opcode_desc(isa, opcode);
 
    if (brw_inst_pred_control(devinfo, inst)) {
       string(file, "(");
@@ -1904,7 +1914,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
       string(file, ") ");
    }
 
-   err |= print_opcode(file, devinfo, opcode);
+   err |= print_opcode(file, isa, opcode);
 
    if (!is_send(opcode))
       err |= control(file, "saturate", saturate, brw_inst_saturate(devinfo, inst),
@@ -1990,7 +2000,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
       format(file, "Pop: %"PRIu64, brw_inst_gfx4_pop_count(devinfo, inst));
    } else if (opcode == BRW_OPCODE_JMPI) {
       pad(file, 16);
-      err |= src1(file, devinfo, inst);
+      err |= src1(file, isa, inst);
    } else if (desc && desc->nsrc == 3) {
       pad(file, 16);
       err |= dest_3src(file, devinfo, inst);
@@ -2006,17 +2016,17 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
    } else if (desc) {
       if (desc->ndst > 0) {
          pad(file, 16);
-         err |= dest(file, devinfo, inst);
+         err |= dest(file, isa, inst);
       }
 
       if (desc->nsrc > 0) {
          pad(file, 32);
-         err |= src0(file, devinfo, inst);
+         err |= src0(file, isa, inst);
       }
 
       if (desc->nsrc > 1) {
          pad(file, 48);
-         err |= src1(file, devinfo, inst);
+         err |= src1(file, isa, inst);
       }
    }
 
@@ -2050,7 +2060,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
          if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
             /* show the indirect descriptor source */
             pad(file, 48);
-            err |= src1(file, devinfo, inst);
+            err |= src1(file, isa, inst);
             pad(file, 64);
          } else {
             has_imm_desc = true;
@@ -2473,7 +2483,7 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
       }
 
       if (devinfo->ver >= 12)
-         err |= swsb(file, devinfo, inst);
+         err |= swsb(file, isa, inst);
 
       err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space);
       err |= control(file, "thread control", thread_ctrl,
diff --git a/src/intel/compiler/brw_disasm_info.c b/src/intel/compiler/brw_disasm_info.c
index 591d1e84fd2..779e25f9db6 100644
--- a/src/intel/compiler/brw_disasm_info.c
+++ b/src/intel/compiler/brw_disasm_info.c
@@ -34,13 +34,13 @@ void
 dump_assembly(void *assembly, int start_offset, int end_offset,
               struct disasm_info *disasm, const unsigned *block_latency)
 {
-   const struct intel_device_info *devinfo = disasm->devinfo;
+   const struct brw_isa_info *isa = disasm->isa;
    const char *last_annotation_string = NULL;
    const void *last_annotation_ir = NULL;
 
    void *mem_ctx = ralloc_context(NULL);
    const struct brw_label *root_label =
-      brw_label_assembly(devinfo, assembly, start_offset, end_offset, mem_ctx);
+      brw_label_assembly(isa, assembly, start_offset, end_offset, mem_ctx);
 
    foreach_list_typed(struct inst_group, group, link, &disasm->group_list) {
       struct exec_node *next_node = exec_node_get_next(&group->link);
@@ -81,7 +81,7 @@ dump_assembly(void *assembly, int start_offset, int end_offset,
             fprintf(stderr, "   %s\n", last_annotation_string);
       }
 
-      brw_disassemble(devinfo, assembly, start_offset, end_offset,
+      brw_disassemble(isa, assembly, start_offset, end_offset,
                       root_label, stderr);
 
       if (group->error) {
@@ -104,12 +104,12 @@ dump_assembly(void *assembly, int start_offset, int end_offset,
 }
 
 struct disasm_info *
-disasm_initialize(const struct intel_device_info *devinfo,
+disasm_initialize(const struct brw_isa_info *isa,
                   const struct cfg_t *cfg)
 {
    struct disasm_info *disasm = ralloc(NULL, struct disasm_info);
    exec_list_make_empty(&disasm->group_list);
-   disasm->devinfo = devinfo;
+   disasm->isa = isa;
    disasm->cfg = cfg;
    disasm->cur_block = 0;
    disasm->use_tail = false;
@@ -129,7 +129,7 @@ void
 disasm_annotate(struct disasm_info *disasm,
                 struct backend_instruction *inst, unsigned offset)
 {
-   const struct intel_device_info *devinfo = disasm->devinfo;
+   const struct intel_device_info *devinfo = disasm->isa->devinfo;
    const struct cfg_t *cfg = disasm->cfg;
 
    struct inst_group *group;
diff --git a/src/intel/compiler/brw_disasm_info.h b/src/intel/compiler/brw_disasm_info.h
index 715b82d0048..c45b98a0209 100644
--- a/src/intel/compiler/brw_disasm_info.h
+++ b/src/intel/compiler/brw_disasm_info.h
@@ -56,7 +56,7 @@ struct inst_group {
 struct disasm_info {
    struct exec_list group_list;
 
-   const struct intel_device_info *devinfo;
+   const struct brw_isa_info *isa;
    const struct cfg_t *cfg;
 
    /** Block index in the cfg. */
@@ -69,7 +69,7 @@ dump_assembly(void *assembly, int start_offset, int end_offset,
               struct disasm_info *disasm, const unsigned *block_latency);
 
 struct disasm_info *
-disasm_initialize(const struct intel_device_info *devinfo,
+disasm_initialize(const struct brw_isa_info *isa,
                   const struct cfg_t *cfg);
 
 struct inst_group *
diff --git a/src/intel/compiler/brw_eu.cpp b/src/intel/compiler/brw_eu.cpp
index cf20b20eabe..cd13d18c2a2 100644
--- a/src/intel/compiler/brw_eu.cpp
+++ b/src/intel/compiler/brw_eu.cpp
@@ -317,12 +317,13 @@ void brw_pop_insn_state( struct brw_codegen *p )
 /***********************************************************************
  */
 void
-brw_init_codegen(const struct intel_device_info *devinfo,
+brw_init_codegen(const struct brw_isa_info *isa,
                  struct brw_codegen *p, void *mem_ctx)
 {
    memset(p, 0, sizeof(*p));
 
-   p->devinfo = devinfo;
+   p->isa = isa;
+   p->devinfo = isa->devinfo;
    p->automatic_exec_sizes = true;
    /*
     * Set the initial instruction store array size to 1024, if found that
@@ -408,7 +409,7 @@ bool brw_try_override_assembly(struct brw_codegen *p, int start_offset,
    }
 
    ASSERTED bool valid =
-      brw_validate_instructions(p->devinfo, p->store,
+      brw_validate_instructions(p->isa, p->store,
                                 start_offset, p->next_insn_offset,
                                 NULL);
    assert(valid);
@@ -465,9 +466,11 @@ brw_create_label(struct brw_label **labels, int offset, void *mem_ctx)
 }
 
 const struct brw_label *
-brw_label_assembly(const struct intel_device_info *devinfo,
+brw_label_assembly(const struct brw_isa_info *isa,
                    const void *assembly, int start, int end, void *mem_ctx)
 {
+   const struct intel_device_info *const devinfo = isa->devinfo;
+
    struct brw_label *root_label = NULL;
 
    int to_bytes_scale = sizeof(brw_inst) / brw_jump_scale(devinfo);
@@ -480,17 +483,17 @@ brw_label_assembly(const struct intel_device_info *devinfo,
 
       if (is_compact) {
          brw_compact_inst *compacted = (brw_compact_inst *)inst;
-         brw_uncompact_instruction(devinfo, &uncompacted, compacted);
+         brw_uncompact_instruction(isa, &uncompacted, compacted);
          inst = &uncompacted;
       }
 
-      if (brw_has_uip(devinfo, brw_inst_opcode(devinfo, inst))) {
+      if (brw_has_uip(devinfo, brw_inst_opcode(isa, inst))) {
          /* Instructions that have UIP also have JIP. */
          brw_create_label(&root_label,
             offset + brw_inst_uip(devinfo, inst) * to_bytes_scale, mem_ctx);
          brw_create_label(&root_label,
             offset + brw_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx);
-      } else if (brw_has_jip(devinfo, brw_inst_opcode(devinfo, inst))) {
+      } else if (brw_has_jip(devinfo, brw_inst_opcode(isa, inst))) {
          int jip;
          if (devinfo->ver >= 7) {
             jip = brw_inst_jip(devinfo, inst);
@@ -512,23 +515,25 @@ brw_label_assembly(const struct intel_device_info *devinfo,
 }
 
 void
-brw_disassemble_with_labels(const struct intel_device_info *devinfo,
+brw_disassemble_with_labels(const struct brw_isa_info *isa,
                             const void *assembly, int start, int end, FILE *out)
 {
    void *mem_ctx = ralloc_context(NULL);
    const struct brw_label *root_label =
-      brw_label_assembly(devinfo, assembly, start, end, mem_ctx);
+      brw_label_assembly(isa, assembly, start, end, mem_ctx);
 
-   brw_disassemble(devinfo, assembly, start, end, root_label, out);
+   brw_disassemble(isa, assembly, start, end, root_label, out);
 
    ralloc_free(mem_ctx);
 }
 
 void
-brw_disassemble(const struct intel_device_info *devinfo,
+brw_disassemble(const struct brw_isa_info *isa,
                 const void *assembly, int start, int end,
                 const struct brw_label *root_label, FILE *out)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    bool dump_hex = INTEL_DEBUG(DEBUG_HEX);
 
    for (int offset = start; offset < end;) {
@@ -564,7 +569,7 @@ brw_disassemble(const struct intel_device_info *devinfo,
             fprintf(out, "%*c", blank_spaces, ' ');
          }
 
-         brw_uncompact_instruction(devinfo, &uncompacted, compacted);
+         brw_uncompact_instruction(isa, &uncompacted, compacted);
          insn = &uncompacted;
       } else {
          if (dump_hex) {
@@ -579,7 +584,7 @@ brw_disassemble(const struct intel_device_info *devinfo,
          }
       }
 
-      brw_disassemble_inst(out, devinfo, insn, compacted, offset, root_label);
+      brw_disassemble_inst(out, isa, insn, compacted, offset, root_label);
 
       if (compacted) {
          offset += sizeof(brw_compact_inst);
@@ -700,6 +705,13 @@ static const struct opcode_desc opcode_descs[] = {
    { BRW_OPCODE_NOP,      96,  "nop",     0,    0,    GFX_GE(GFX12) }
 };
 
+void
+brw_init_isa_info(struct brw_isa_info *isa,
+                  const struct intel_device_info *devinfo)
+{
+   isa->devinfo = devinfo;
+}
+
 /**
  * Look up the opcode_descs[] entry with \p key member matching \p k which is
  * supported by the device specified by \p devinfo, or NULL if there is no
@@ -743,12 +755,12 @@ lookup_opcode_desc(gfx_ver *index_ver,
  * generation, or NULL if the opcode is not supported by the device.
  */
 const struct opcode_desc *
-brw_opcode_desc(const struct intel_device_info *devinfo, enum opcode opcode)
+brw_opcode_desc(const struct brw_isa_info *isa, enum opcode opcode)
 {
    static thread_local gfx_ver index_ver = {};
    static thread_local const opcode_desc *index_descs[NUM_BRW_OPCODES];
    return lookup_opcode_desc(&index_ver, index_descs, ARRAY_SIZE(index_descs),
-                             &opcode_desc::ir, devinfo, opcode);
+                             &opcode_desc::ir, isa->devinfo, opcode);
 }
 
 /**
@@ -756,10 +768,10 @@ brw_opcode_desc(const struct intel_device_info *devinfo, enum opcode opcode)
  * generation, or NULL if the opcode is not supported by the device.
  */
 const struct opcode_desc *
-brw_opcode_desc_from_hw(const struct intel_device_info *devinfo, unsigned hw)
+brw_opcode_desc_from_hw(const struct brw_isa_info *isa, unsigned hw)
 {
    static thread_local gfx_ver index_ver = {};
    static thread_local const opcode_desc *index_descs[128];
    return lookup_opcode_desc(&index_ver, index_descs, ARRAY_SIZE(index_descs),
-                             &opcode_desc::hw, devinfo, hw);
+                             &opcode_desc::hw, isa->devinfo, hw);
 }
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 979ed4b8403..72c0bc8682d 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -113,6 +113,7 @@ struct brw_codegen {
    bool automatic_exec_sizes;
 
    bool single_program_flow;
+   const struct brw_isa_info *isa;
    const struct intel_device_info *devinfo;
 
    /* Control flow stacks:
@@ -174,22 +175,22 @@ void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
 void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
 void brw_set_default_swsb(struct brw_codegen *p, struct tgl_swsb value);
 
-void brw_init_codegen(const struct intel_device_info *, struct brw_codegen *p,
-		      void *mem_ctx);
+void brw_init_codegen(const struct brw_isa_info *isa,
+                      struct brw_codegen *p, void *mem_ctx);
 bool brw_has_jip(const struct intel_device_info *devinfo, enum opcode opcode);
 bool brw_has_uip(const struct intel_device_info *devinfo, enum opcode opcode);
 const struct brw_label *brw_find_label(const struct brw_label *root, int offset);
 void brw_create_label(struct brw_label **labels, int offset, void *mem_ctx);
-int brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
+int brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa,
                          const struct brw_inst *inst, bool is_compacted,
                          int offset, const struct brw_label *root_label);
 const struct
-brw_label *brw_label_assembly(const struct intel_device_info *devinfo,
+brw_label *brw_label_assembly(const struct brw_isa_info *isa,
                               const void *assembly, int start, int end,
                               void *mem_ctx);
-void brw_disassemble_with_labels(const struct intel_device_info *devinfo,
+void brw_disassemble_with_labels(const struct brw_isa_info *isa,
                                  const void *assembly, int start, int end, FILE *out);
-void brw_disassemble(const struct intel_device_info *devinfo,
+void brw_disassemble(const struct brw_isa_info *isa,
                      const void *assembly, int start, int end,
                      const struct brw_label *root_label, FILE *out);
 const struct brw_shader_reloc *brw_get_shader_relocs(struct brw_codegen *p,
@@ -1814,7 +1815,7 @@ brw_float_controls_mode(struct brw_codegen *p,
                         unsigned mode, unsigned mask);
 
 void
-brw_update_reloc_imm(const struct intel_device_info *devinfo,
+brw_update_reloc_imm(const struct brw_isa_info *isa,
                      brw_inst *inst,
                      uint32_t value);
 
@@ -1871,19 +1872,19 @@ enum brw_conditional_mod brw_swap_cmod(enum brw_conditional_mod cmod);
 /* brw_eu_compact.c */
 void brw_compact_instructions(struct brw_codegen *p, int start_offset,
                               struct disasm_info *disasm);
-void brw_uncompact_instruction(const struct intel_device_info *devinfo,
+void brw_uncompact_instruction(const struct brw_isa_info *isa,
                                brw_inst *dst, brw_compact_inst *src);
-bool brw_try_compact_instruction(const struct intel_device_info *devinfo,
+bool brw_try_compact_instruction(const struct brw_isa_info *isa,
                                  brw_compact_inst *dst, const brw_inst *src);
 
-void brw_debug_compact_uncompact(const struct intel_device_info *devinfo,
+void brw_debug_compact_uncompact(const struct brw_isa_info *isa,
                                  brw_inst *orig, brw_inst *uncompacted);
 
 /* brw_eu_validate.c */
-bool brw_validate_instruction(const struct intel_device_info *devinfo,
+bool brw_validate_instruction(const struct brw_isa_info *isa,
                               const brw_inst *inst, int offset,
                               struct disasm_info *disasm);
-bool brw_validate_instructions(const struct intel_device_info *devinfo,
+bool brw_validate_instructions(const struct brw_isa_info *isa,
                                const void *assembly, int start_offset, int end_offset,
                                struct disasm_info *disasm);
 
diff --git a/src/intel/compiler/brw_eu_compact.c b/src/intel/compiler/brw_eu_compact.c
index e034d6f025f..0e2995f9def 100644
--- a/src/intel/compiler/brw_eu_compact.c
+++ b/src/intel/compiler/brw_eu_compact.c
@@ -1065,7 +1065,7 @@ static const uint32_t gfx12_3src_subreg_table[32] = {
 };
 
 struct compaction_state {
-   const struct intel_device_info *devinfo;
+   const struct brw_isa_info *isa;
    const uint32_t *control_index_table;
    const uint32_t *datatype_table;
    const uint16_t *subreg_table;
@@ -1074,13 +1074,13 @@ struct compaction_state {
 };
 
 static void compaction_state_init(struct compaction_state *c,
-                                  const struct intel_device_info *devinfo);
+                                  const struct brw_isa_info *isa);
 
 static bool
 set_control_index(const struct compaction_state *c,
                   brw_compact_inst *dst, const brw_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    uint32_t uncompacted; /* 17b/G45; 19b/IVB+; 21b/TGL+ */
 
    if (devinfo->ver >= 12) {
@@ -1125,7 +1125,7 @@ static bool
 set_datatype_index(const struct compaction_state *c, brw_compact_inst *dst,
                    const brw_inst *src, bool is_immediate)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    uint32_t uncompacted; /* 18b/G45+; 21b/BDW+; 20b/TGL+ */
 
    if (devinfo->ver >= 12) {
@@ -1168,7 +1168,7 @@ static bool
 set_subreg_index(const struct compaction_state *c, brw_compact_inst *dst,
                  const brw_inst *src, bool is_immediate)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    uint16_t uncompacted; /* 15b */
 
    if (devinfo->ver >= 12) {
@@ -1199,7 +1199,7 @@ static bool
 set_src0_index(const struct compaction_state *c, brw_compact_inst *dst,
                const brw_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    uint16_t uncompacted; /* 12b */
    int table_len;
 
@@ -1229,7 +1229,7 @@ static bool
 set_src1_index(const struct compaction_state *c, brw_compact_inst *dst,
                const brw_inst *src, bool is_immediate, unsigned imm)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    if (is_immediate) {
       if (devinfo->ver >= 12) {
          /* src1 index takes the low 4 bits of the 12-bit compacted value */
@@ -1437,11 +1437,13 @@ set_3src_subreg_index(const struct intel_device_info *devinfo,
 }
 
 static bool
-has_unmapped_bits(const struct intel_device_info *devinfo, const brw_inst *src)
+has_unmapped_bits(const struct brw_isa_info *isa, const brw_inst *src)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    /* EOT can only be mapped on a send if the src1 is an immediate */
-   if ((brw_inst_opcode(devinfo, src) == BRW_OPCODE_SENDC ||
-        brw_inst_opcode(devinfo, src) == BRW_OPCODE_SEND) &&
+   if ((brw_inst_opcode(isa, src) == BRW_OPCODE_SENDC ||
+        brw_inst_opcode(isa, src) == BRW_OPCODE_SEND) &&
        brw_inst_eot(devinfo, src))
       return true;
 
@@ -1696,8 +1698,10 @@ has_immediate(const struct intel_device_info *devinfo, const brw_inst *inst,
  * compaction.
  */
 static brw_inst
-precompact(const struct intel_device_info *devinfo, brw_inst inst)
+precompact(const struct brw_isa_info *isa, brw_inst inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    /* In XeHP the compaction tables removed the entries for source regions
     * <8;8,1> giving preference to <1;1,0> as the way to indicate
     * sequential elements, so convert to those before compacting.
@@ -1753,7 +1757,7 @@ precompact(const struct intel_device_info *devinfo, brw_inst inst)
     */
    if (devinfo->ver >= 6 &&
        !(devinfo->platform == INTEL_PLATFORM_HSW &&
-         brw_inst_opcode(devinfo, &inst) == BRW_OPCODE_DIM) &&
+         brw_inst_opcode(isa, &inst) == BRW_OPCODE_DIM) &&
        !(devinfo->ver >= 8 &&
          (brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_DF ||
           brw_inst_src0_type(devinfo, &inst) == BRW_REGISTER_TYPE_UQ ||
@@ -1815,12 +1819,12 @@ static bool
 try_compact_instruction(const struct compaction_state *c,
                         brw_compact_inst *dst, const brw_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    brw_compact_inst temp;
 
    assert(brw_inst_cmpt_control(devinfo, src) == 0);
 
-   if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) {
+   if (is_3src(c->isa, brw_inst_opcode(c->isa, src))) {
       if (devinfo->ver >= 8) {
          memset(&temp, 0, sizeof(temp));
          if (brw_try_compact_3src_instruction(devinfo, &temp, src)) {
@@ -1850,7 +1854,7 @@ try_compact_instruction(const struct compaction_state *c,
          return false;
    }
 
-   if (has_unmapped_bits(devinfo, src))
+   if (has_unmapped_bits(c->isa, src))
       return false;
 
    memset(&temp, 0, sizeof(temp));
@@ -1919,11 +1923,11 @@ try_compact_instruction(const struct compaction_state *c,
 }
 
 bool
-brw_try_compact_instruction(const struct intel_device_info *devinfo,
+brw_try_compact_instruction(const struct brw_isa_info *isa,
                             brw_compact_inst *dst, const brw_inst *src)
 {
    struct compaction_state c;
-   compaction_state_init(&c, devinfo);
+   compaction_state_init(&c, isa);
    return try_compact_instruction(&c, dst, src);
 }
 
@@ -1931,7 +1935,7 @@ static void
 set_uncompacted_control(const struct compaction_state *c, brw_inst *dst,
                         brw_compact_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    uint32_t uncompacted =
       c->control_index_table[brw_compact_inst_control_index(devinfo, src)];
 
@@ -1965,7 +1969,7 @@ static void
 set_uncompacted_datatype(const struct compaction_state *c, brw_inst *dst,
                          brw_compact_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    uint32_t uncompacted =
       c->datatype_table[brw_compact_inst_datatype_index(devinfo, src)];
 
@@ -1994,7 +1998,7 @@ static void
 set_uncompacted_subreg(const struct compaction_state *c, brw_inst *dst,
                        brw_compact_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    uint16_t uncompacted =
       c->subreg_table[brw_compact_inst_subreg_index(devinfo, src)];
 
@@ -2013,7 +2017,7 @@ static void
 set_uncompacted_src0(const struct compaction_state *c, brw_inst *dst,
                      brw_compact_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    uint32_t compacted = brw_compact_inst_src0_index(devinfo, src);
    uint16_t uncompacted = c->src0_index_table[compacted];
 
@@ -2032,7 +2036,7 @@ static void
 set_uncompacted_src1(const struct compaction_state *c, brw_inst *dst,
                      brw_compact_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    uint16_t uncompacted =
       c->src1_index_table[brw_compact_inst_src1_index(devinfo, src)];
 
@@ -2051,7 +2055,7 @@ static void
 set_uncompacted_3src_control_index(const struct compaction_state *c,
                                    brw_inst *dst, brw_compact_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    assert(devinfo->ver >= 8);
 
    if (devinfo->verx10 >= 125) {
@@ -2179,7 +2183,7 @@ static void
 brw_uncompact_3src_instruction(const struct compaction_state *c,
                                brw_inst *dst, brw_compact_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    assert(devinfo->ver >= 8);
 
 #define uncompact(field) \
@@ -2227,12 +2231,12 @@ static void
 uncompact_instruction(const struct compaction_state *c, brw_inst *dst,
                       brw_compact_inst *src)
 {
-   const struct intel_device_info *devinfo = c->devinfo;
+   const struct intel_device_info *devinfo = c->isa->devinfo;
    memset(dst, 0, sizeof(*dst));
 
    if (devinfo->ver >= 8 &&
-       is_3src(devinfo, brw_opcode_decode(
-                  devinfo, brw_compact_inst_3src_hw_opcode(devinfo, src)))) {
+       is_3src(c->isa, brw_opcode_decode(c->isa,
+                  brw_compact_inst_3src_hw_opcode(devinfo, src)))) {
       brw_uncompact_3src_instruction(c, dst, src);
       return;
    }
@@ -2287,26 +2291,27 @@ uncompact_instruction(const struct compaction_state *c, brw_inst *dst,
 }
 
 void
-brw_uncompact_instruction(const struct intel_device_info *devinfo,
+brw_uncompact_instruction(const struct brw_isa_info *isa,
                           brw_inst *dst, brw_compact_inst *src)
 {
    struct compaction_state c;
-   compaction_state_init(&c, devinfo);
+   compaction_state_init(&c, isa);
    uncompact_instruction(&c, dst, src);
 }
 
-void brw_debug_compact_uncompact(const struct intel_device_info *devinfo,
-                                 brw_inst *orig,
-                                 brw_inst *uncompacted)
+void
+brw_debug_compact_uncompact(const struct brw_isa_info *isa,
+                            brw_inst *orig,
+                            brw_inst *uncompacted)
 {
    fprintf(stderr, "Instruction compact/uncompact changed (gen%d):\n",
-           devinfo->ver);
+           isa->devinfo->ver);
 
    fprintf(stderr, "  before: ");
-   brw_disassemble_inst(stderr, devinfo, orig, true, 0, NULL);
+   brw_disassemble_inst(stderr, isa, orig, true, 0, NULL);
 
    fprintf(stderr, "  after:  ");
-   brw_disassemble_inst(stderr, devinfo, uncompacted, false, 0, NULL);
+   brw_disassemble_inst(stderr, isa, uncompacted, false, 0, NULL);
 
    uint32_t *before_bits = (uint32_t *)orig;
    uint32_t *after_bits = (uint32_t *)uncompacted;
@@ -2332,9 +2337,11 @@ compacted_between(int old_ip, int old_target_ip, int *compacted_counts)
 }
 
 static void
-update_uip_jip(const struct intel_device_info *devinfo, brw_inst *insn,
+update_uip_jip(const struct brw_isa_info *isa, brw_inst *insn,
                int this_old_ip, int *compacted_counts)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    /* JIP and UIP are in units of:
     *    - bytes on Gfx8+; and
     *    - compacted instructions on Gfx6+.
@@ -2347,9 +2354,9 @@ update_uip_jip(const struct intel_device_info *devinfo, brw_inst *insn,
                                       compacted_counts);
    brw_inst_set_jip(devinfo, insn, jip_compacted << shift);
 
-   if (brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ENDIF ||
-       brw_inst_opcode(devinfo, insn) == BRW_OPCODE_WHILE ||
-       (brw_inst_opcode(devinfo, insn) == BRW_OPCODE_ELSE && devinfo->ver <= 7))
+   if (brw_inst_opcode(isa, insn) == BRW_OPCODE_ENDIF ||
+       brw_inst_opcode(isa, insn) == BRW_OPCODE_WHILE ||
+       (brw_inst_opcode(isa, insn) == BRW_OPCODE_ELSE && devinfo->ver <= 7))
       return;
 
    int32_t uip_compacted = brw_inst_uip(devinfo, insn) >> shift;
@@ -2384,8 +2391,10 @@ update_gfx4_jump_count(const struct intel_device_info *devinfo, brw_inst *insn,
 
 static void
 compaction_state_init(struct compaction_state *c,
-                      const struct intel_device_info *devinfo)
+                      const struct brw_isa_info *isa)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    assert(g45_control_index_table[ARRAY_SIZE(g45_control_index_table) - 1] != 0);
    assert(g45_datatype_table[ARRAY_SIZE(g45_datatype_table) - 1] != 0);
    assert(g45_subreg_table[ARRAY_SIZE(g45_subreg_table) - 1] != 0);
@@ -2411,7 +2420,7 @@ compaction_state_init(struct compaction_state *c,
    assert(xehp_src0_index_table[ARRAY_SIZE(xehp_src0_index_table) - 1] != 0);
    assert(xehp_src1_index_table[ARRAY_SIZE(xehp_src1_index_table) - 1] != 0);
 
-   c->devinfo = devinfo;
+   c->isa = isa;
    switch (devinfo->ver) {
    case 12:
       c->control_index_table = gfx12_control_index_table;;
@@ -2490,7 +2499,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
       return;
 
    struct compaction_state c;
-   compaction_state_init(&c, devinfo);
+   compaction_state_init(&c, p->isa);
 
    int offset = 0;
    int compacted_count = 0;
@@ -2502,7 +2511,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
       old_ip[offset / sizeof(brw_compact_inst)] = src_offset / sizeof(brw_inst);
       compacted_counts[src_offset / sizeof(brw_inst)] = compacted_count;
 
-      brw_inst inst = precompact(devinfo, *src);
+      brw_inst inst = precompact(p->isa, *src);
       brw_inst saved = inst;
 
       if (try_compact_instruction(&c, dst, &inst)) {
@@ -2512,7 +2521,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
             brw_inst uncompacted;
             uncompact_instruction(&c, &uncompacted, dst);
             if (memcmp(&saved, &uncompacted, sizeof(uncompacted))) {
-               brw_debug_compact_uncompact(devinfo, &saved, &uncompacted);
+               brw_debug_compact_uncompact(p->isa, &saved, &uncompacted);
             }
          }
 
@@ -2524,7 +2533,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
             brw_compact_inst *align = store + offset;
             memset(align, 0, sizeof(*align));
             brw_compact_inst_set_hw_opcode(
-               devinfo, align, brw_opcode_encode(devinfo, BRW_OPCODE_NENOP));
+               devinfo, align, brw_opcode_encode(p->isa, BRW_OPCODE_NENOP));
             brw_compact_inst_set_cmpt_control(devinfo, align, true);
             offset += sizeof(brw_compact_inst);
             compacted_count--;
@@ -2558,12 +2567,12 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
       int this_old_ip = old_ip[offset / sizeof(brw_compact_inst)];
       int this_compacted_count = compacted_counts[this_old_ip];
 
-      switch (brw_inst_opcode(devinfo, insn)) {
+      switch (brw_inst_opcode(p->isa, insn)) {
       case BRW_OPCODE_BREAK:
       case BRW_OPCODE_CONTINUE:
       case BRW_OPCODE_HALT:
          if (devinfo->ver >= 6) {
-            update_uip_jip(devinfo, insn, this_old_ip, compacted_counts);
+            update_uip_jip(p->isa, insn, this_old_ip, compacted_counts);
          } else {
             update_gfx4_jump_count(devinfo, insn, this_old_ip,
                                    compacted_counts);
@@ -2581,14 +2590,14 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
                uncompact_instruction(&c, &uncompacted,
                                      (brw_compact_inst *)insn);
 
-               update_uip_jip(devinfo, &uncompacted, this_old_ip,
+               update_uip_jip(p->isa, &uncompacted, this_old_ip,
                               compacted_counts);
 
                bool ret = try_compact_instruction(&c, (brw_compact_inst *)insn,
                                                   &uncompacted);
                assert(ret); (void)ret;
             } else {
-               update_uip_jip(devinfo, insn, this_old_ip, compacted_counts);
+               update_uip_jip(p->isa, insn, this_old_ip, compacted_counts);
             }
          } else if (devinfo->ver == 6) {
             assert(!brw_inst_cmpt_control(devinfo, insn));
@@ -2642,7 +2651,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
       brw_compact_inst *align = store + offset;
       memset(align, 0, sizeof(*align));
       brw_compact_inst_set_hw_opcode(
-         devinfo, align, brw_opcode_encode(devinfo, BRW_OPCODE_NOP));
+         devinfo, align, brw_opcode_encode(p->isa, BRW_OPCODE_NOP));
       brw_compact_inst_set_cmpt_control(devinfo, align, true);
       p->next_insn_offset += sizeof(brw_compact_inst);
    }
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 150f5f40e1e..28360abed70 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -110,8 +110,8 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
    gfx7_convert_mrf_to_grf(p, &dest);
 
    if (devinfo->ver >= 12 &&
-       (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
-        brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC)) {
+       (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND ||
+        brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC)) {
       assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
              dest.file == BRW_ARCHITECTURE_REGISTER_FILE);
       assert(dest.address_mode == BRW_ADDRESS_DIRECT);
@@ -123,8 +123,8 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
       brw_inst_set_dst_reg_file(devinfo, inst, dest.file);
       brw_inst_set_dst_da_reg_nr(devinfo, inst, dest.nr);
 
-   } else if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||
-              brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC) {
+   } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS ||
+              brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC) {
       assert(devinfo->ver < 12);
       assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
              dest.file == BRW_ARCHITECTURE_REGISTER_FILE);
@@ -218,10 +218,10 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
    gfx7_convert_mrf_to_grf(p, &reg);
 
    if (devinfo->ver >= 6 &&
-       (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
-        brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC ||
-        brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||
-        brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC)) {
+       (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND ||
+        brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC ||
+        brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS ||
+        brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC)) {
       /* Any source modifiers or regions will be ignored, since this just
        * identifies the MRF/GRF to start reading the message contents from.
        * Check for some likely failures.
@@ -232,8 +232,8 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
    }
 
    if (devinfo->ver >= 12 &&
-       (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
-        brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC)) {
+       (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND ||
+        brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC)) {
       assert(reg.file != BRW_IMMEDIATE_VALUE);
       assert(reg.address_mode == BRW_ADDRESS_DIRECT);
       assert(reg.subnr == 0);
@@ -244,8 +244,8 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
       brw_inst_set_send_src0_reg_file(devinfo, inst, reg.file);
       brw_inst_set_src0_da_reg_nr(devinfo, inst, reg.nr);
 
-   } else if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||
-              brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC) {
+   } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS ||
+              brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC) {
       assert(reg.file == BRW_GENERAL_REGISTER_FILE);
       assert(reg.address_mode == BRW_ADDRESS_DIRECT);
       assert(reg.subnr % 16 == 0);
@@ -263,7 +263,7 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
 
       if (reg.file == BRW_IMMEDIATE_VALUE) {
          if (reg.type == BRW_REGISTER_TYPE_DF ||
-             brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM)
+             brw_inst_opcode(p->isa, inst) == BRW_OPCODE_DIM)
             brw_inst_set_imm_df(devinfo, inst, reg.df);
          else if (reg.type == BRW_REGISTER_TYPE_UQ ||
                   reg.type == BRW_REGISTER_TYPE_Q)
@@ -349,11 +349,11 @@ brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
    if (reg.file == BRW_GENERAL_REGISTER_FILE)
       assert(reg.nr < 128);
 
-   if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDS ||
-       brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDSC ||
+   if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDS ||
+       brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDSC ||
        (devinfo->ver >= 12 &&
-        (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
-         brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC))) {
+        (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND ||
+         brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC))) {
       assert(reg.file == BRW_GENERAL_REGISTER_FILE ||
              reg.file == BRW_ARCHITECTURE_REGISTER_FILE);
       assert(reg.address_mode == BRW_ADDRESS_DIRECT);
@@ -456,8 +456,8 @@ brw_set_desc_ex(struct brw_codegen *p, brw_inst *inst,
                 unsigned desc, unsigned ex_desc)
 {
    const struct intel_device_info *devinfo = p->devinfo;
-   assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND ||
-          brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SENDC);
+   assert(brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SEND ||
+          brw_inst_opcode(p->isa, inst) == BRW_OPCODE_SENDC);
    if (devinfo->ver < 12)
       brw_inst_set_src1_file_type(devinfo, inst,
                                   BRW_IMMEDIATE_VALUE, BRW_REGISTER_TYPE_UD);
@@ -610,10 +610,12 @@ gfx7_set_dp_scratch_message(struct brw_codegen *p,
 }
 
 static void
-brw_inst_set_state(const struct intel_device_info *devinfo,
+brw_inst_set_state(const struct brw_isa_info *isa,
                    brw_inst *insn,
                    const struct brw_insn_state *state)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    brw_inst_set_exec_size(devinfo, insn, state->exec_size);
    brw_inst_set_group(devinfo, insn, state->group);
    brw_inst_set_compression(devinfo, insn, state->compressed);
@@ -625,7 +627,7 @@ brw_inst_set_state(const struct intel_device_info *devinfo,
    brw_inst_set_pred_control(devinfo, insn, state->predicate);
    brw_inst_set_pred_inv(devinfo, insn, state->pred_inv);
 
-   if (is_3src(devinfo, brw_inst_opcode(devinfo, insn)) &&
+   if (is_3src(isa, brw_inst_opcode(isa, insn)) &&
        state->access_mode == BRW_ALIGN_16) {
       brw_inst_set_3src_a16_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
       if (devinfo->ver >= 7)
@@ -694,14 +696,13 @@ brw_append_data(struct brw_codegen *p, void *data,
 brw_inst *
 brw_next_insn(struct brw_codegen *p, unsigned opcode)
 {
-   const struct intel_device_info *devinfo = p->devinfo;
    brw_inst *insn = brw_append_insns(p, 1, sizeof(brw_inst));
 
    memset(insn, 0, sizeof(*insn));
-   brw_inst_set_opcode(devinfo, insn, opcode);
+   brw_inst_set_opcode(p->isa, insn, opcode);
 
    /* Apply the default instruction state */
-   brw_inst_set_state(devinfo, insn, p->current);
+   brw_inst_set_state(p->isa, insn, p->current);
 
    return insn;
 }
@@ -1333,7 +1334,7 @@ void brw_NOP(struct brw_codegen *p)
 {
    brw_inst *insn = next_insn(p, BRW_OPCODE_NOP);
    memset(insn, 0, sizeof(*insn));
-   brw_inst_set_opcode(p->devinfo, insn, BRW_OPCODE_NOP);
+   brw_inst_set_opcode(p->isa, insn, BRW_OPCODE_NOP);
 }
 
 void brw_SYNC(struct brw_codegen *p, enum tgl_sync_function func)
@@ -1501,8 +1502,8 @@ convert_IF_ELSE_to_ADD(struct brw_codegen *p,
    brw_inst *next_inst = &p->store[p->nr_insn];
 
    assert(p->single_program_flow);
-   assert(if_inst != NULL && brw_inst_opcode(devinfo, if_inst) == BRW_OPCODE_IF);
-   assert(else_inst == NULL || brw_inst_opcode(devinfo, else_inst) == BRW_OPCODE_ELSE);
+   assert(if_inst != NULL && brw_inst_opcode(p->isa, if_inst) == BRW_OPCODE_IF);
+   assert(else_inst == NULL || brw_inst_opcode(p->isa, else_inst) == BRW_OPCODE_ELSE);
    assert(brw_inst_exec_size(devinfo, if_inst) == BRW_EXECUTE_1);
 
    /* Convert IF to an ADD instruction that moves the instruction pointer
@@ -1513,14 +1514,14 @@ convert_IF_ELSE_to_ADD(struct brw_codegen *p,
     * stack operations, and if we're currently executing, we just want to
     * continue normally.
     */
-   brw_inst_set_opcode(devinfo, if_inst, BRW_OPCODE_ADD);
+   brw_inst_set_opcode(p->isa, if_inst, BRW_OPCODE_ADD);
    brw_inst_set_pred_inv(devinfo, if_inst, true);
 
    if (else_inst != NULL) {
       /* Convert ELSE to an ADD instruction that points where the ENDIF
        * would be.
        */
-      brw_inst_set_opcode(devinfo, else_inst, BRW_OPCODE_ADD);
+      brw_inst_set_opcode(p->isa, else_inst, BRW_OPCODE_ADD);
 
       brw_inst_set_imm_ud(devinfo, if_inst, (else_inst - if_inst + 1) * 16);
       brw_inst_set_imm_ud(devinfo, else_inst, (next_inst - else_inst) * 16);
@@ -1553,13 +1554,13 @@ patch_IF_ELSE(struct brw_codegen *p,
    if (devinfo->ver < 6)
       assert(!p->single_program_flow);
 
-   assert(if_inst != NULL && brw_inst_opcode(devinfo, if_inst) == BRW_OPCODE_IF);
+   assert(if_inst != NULL && brw_inst_opcode(p->isa, if_inst) == BRW_OPCODE_IF);
    assert(endif_inst != NULL);
-   assert(else_inst == NULL || brw_inst_opcode(devinfo, else_inst) == BRW_OPCODE_ELSE);
+   assert(else_inst == NULL || brw_inst_opcode(p->isa, else_inst) == BRW_OPCODE_ELSE);
 
    unsigned br = brw_jump_scale(devinfo);
 
-   assert(brw_inst_opcode(devinfo, endif_inst) == BRW_OPCODE_ENDIF);
+   assert(brw_inst_opcode(p->isa, endif_inst) == BRW_OPCODE_ENDIF);
    brw_inst_set_exec_size(devinfo, endif_inst, brw_inst_exec_size(devinfo, if_inst));
 
    if (else_inst == NULL) {
@@ -1568,7 +1569,7 @@ patch_IF_ELSE(struct brw_codegen *p,
 	 /* Turn it into an IFF, which means no mask stack operations for
 	  * all-false and jumping past the ENDIF.
 	  */
-         brw_inst_set_opcode(devinfo, if_inst, BRW_OPCODE_IFF);
+         brw_inst_set_opcode(p->isa, if_inst, BRW_OPCODE_IFF);
          brw_inst_set_gfx4_jump_count(devinfo, if_inst,
                                       br * (endif_inst - if_inst + 1));
          brw_inst_set_gfx4_pop_count(devinfo, if_inst, 0);
@@ -1695,7 +1696,7 @@ brw_ENDIF(struct brw_codegen *p)
    /* Pop the IF and (optional) ELSE instructions from the stack */
    p->if_depth_in_loop[p->loop_stack_depth]--;
    tmp = pop_if_stack(p);
-   if (brw_inst_opcode(devinfo, tmp) == BRW_OPCODE_ELSE) {
+   if (brw_inst_opcode(p->isa, tmp) == BRW_OPCODE_ELSE) {
       else_inst = tmp;
       tmp = pop_if_stack(p);
    }
@@ -1885,10 +1886,10 @@ brw_patch_break_cont(struct brw_codegen *p, brw_inst *while_inst)
        * been patched because it's part of a loop inside of the one we're
        * patching.
        */
-      if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_BREAK &&
+      if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_BREAK &&
           brw_inst_gfx4_jump_count(devinfo, inst) == 0) {
          brw_inst_set_gfx4_jump_count(devinfo, inst, br*((while_inst - inst) + 1));
-      } else if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_CONTINUE &&
+      } else if (brw_inst_opcode(p->isa, inst) == BRW_OPCODE_CONTINUE &&
                  brw_inst_gfx4_jump_count(devinfo, inst) == 0) {
          brw_inst_set_gfx4_jump_count(devinfo, inst, br * (while_inst - inst));
       }
@@ -1938,7 +1939,7 @@ brw_WHILE(struct brw_codegen *p)
 	 insn = next_insn(p, BRW_OPCODE_WHILE);
          do_insn = get_inner_do_insn(p);
 
-         assert(brw_inst_opcode(devinfo, do_insn) == BRW_OPCODE_DO);
+         assert(brw_inst_opcode(p->isa, do_insn) == BRW_OPCODE_DO);
 
 	 brw_set_dest(p, insn, brw_ip_reg());
 	 brw_set_src0(p, insn, brw_ip_reg());
@@ -1969,7 +1970,7 @@ void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx)
    if (devinfo->ver >= 5)
       jmpi = 2;
 
-   assert(brw_inst_opcode(devinfo, jmp_insn) == BRW_OPCODE_JMPI);
+   assert(brw_inst_opcode(p->isa, jmp_insn) == BRW_OPCODE_JMPI);
    assert(brw_inst_src1_reg_file(devinfo, jmp_insn) == BRW_IMMEDIATE_VALUE);
 
    brw_inst_set_gfx4_jump_count(devinfo, jmp_insn,
@@ -2914,7 +2915,7 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset)
         offset = next_offset(devinfo, store, offset)) {
       brw_inst *insn = store + offset;
 
-      switch (brw_inst_opcode(devinfo, insn)) {
+      switch (brw_inst_opcode(p->isa, insn)) {
       case BRW_OPCODE_IF:
          depth++;
          break;
@@ -2964,7 +2965,7 @@ brw_find_loop_end(struct brw_codegen *p, int start_offset)
         offset = next_offset(devinfo, store, offset)) {
       brw_inst *insn = store + offset;
 
-      if (brw_inst_opcode(devinfo, insn) == BRW_OPCODE_WHILE) {
+      if (brw_inst_opcode(p->isa, insn) == BRW_OPCODE_WHILE) {
 	 if (while_jumps_before_offset(devinfo, insn, offset, start_offset))
 	    return offset;
       }
@@ -2992,7 +2993,7 @@ brw_set_uip_jip(struct brw_codegen *p, int start_offset)
       brw_inst *insn = store + offset;
       assert(brw_inst_cmpt_control(devinfo, insn) == 0);
 
-      switch (brw_inst_opcode(devinfo, insn)) {
+      switch (brw_inst_opcode(p->isa, insn)) {
       case BRW_OPCODE_BREAK: {
          int block_end_offset = brw_find_next_block_end(p, offset);
          assert(block_end_offset != 0);
@@ -3718,12 +3719,14 @@ brw_float_controls_mode(struct brw_codegen *p,
 }
 
 void
-brw_update_reloc_imm(const struct intel_device_info *devinfo,
+brw_update_reloc_imm(const struct brw_isa_info *isa,
                      brw_inst *inst,
                      uint32_t value)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    /* Sanity check that the instruction is a MOV of an immediate */
-   assert(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MOV);
+   assert(brw_inst_opcode(isa, inst) == BRW_OPCODE_MOV);
    assert(brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE);
 
    /* If it was compacted, we can't safely rewrite */
diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c
index a22e8719ddc..09c970b2d25 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -79,7 +79,7 @@ contains(const struct string haystack, const struct string needle)
 
 #define CHECK(func, args...)                             \
    do {                                                  \
-      struct string __msg = func(devinfo, inst, ##args); \
+      struct string __msg = func(isa, inst, ##args); \
       if (__msg.str) {                                   \
          cat(&error_msg, __msg);                         \
          free(__msg.str);                                \
@@ -90,9 +90,9 @@ contains(const struct string haystack, const struct string needle)
 #define WIDTH(width)   (1 << (width))
 
 static bool
-inst_is_send(const struct intel_device_info *devinfo, const brw_inst *inst)
+inst_is_send(const struct brw_isa_info *isa, const brw_inst *inst)
 {
-   switch (brw_inst_opcode(devinfo, inst)) {
+   switch (brw_inst_opcode(isa, inst)) {
    case BRW_OPCODE_SEND:
    case BRW_OPCODE_SENDC:
    case BRW_OPCODE_SENDS:
@@ -104,13 +104,14 @@ inst_is_send(const struct intel_device_info *devinfo, const brw_inst *inst)
 }
 
 static bool
-inst_is_split_send(const struct intel_device_info *devinfo,
-                   const brw_inst *inst)
+inst_is_split_send(const struct brw_isa_info *isa, const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    if (devinfo->ver >= 12) {
-      return inst_is_send(devinfo, inst);
+      return inst_is_send(isa, inst);
    } else {
-      switch (brw_inst_opcode(devinfo, inst)) {
+      switch (brw_inst_opcode(isa, inst)) {
       case BRW_OPCODE_SENDS:
       case BRW_OPCODE_SENDSC:
          return true;
@@ -133,16 +134,20 @@ signed_type(unsigned type)
 }
 
 static enum brw_reg_type
-inst_dst_type(const struct intel_device_info *devinfo, const brw_inst *inst)
+inst_dst_type(const struct brw_isa_info *isa, const brw_inst *inst)
 {
-   return (devinfo->ver < 12 || !inst_is_send(devinfo, inst)) ?
+   const struct intel_device_info *devinfo = isa->devinfo;
+
+   return (devinfo->ver < 12 || !inst_is_send(isa, inst)) ?
       brw_inst_dst_type(devinfo, inst) : BRW_REGISTER_TYPE_D;
 }
 
 static bool
-inst_is_raw_move(const struct intel_device_info *devinfo, const brw_inst *inst)
+inst_is_raw_move(const struct brw_isa_info *isa, const brw_inst *inst)
 {
-   unsigned dst_type = signed_type(inst_dst_type(devinfo, inst));
+   const struct intel_device_info *devinfo = isa->devinfo;
+
+   unsigned dst_type = signed_type(inst_dst_type(isa, inst));
    unsigned src_type = signed_type(brw_inst_src0_type(devinfo, inst));
 
    if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
@@ -157,7 +162,7 @@ inst_is_raw_move(const struct intel_device_info *devinfo, const brw_inst *inst)
       return false;
    }
 
-   return brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MOV &&
+   return brw_inst_opcode(isa, inst) == BRW_OPCODE_MOV &&
           brw_inst_saturate(devinfo, inst) == 0 &&
           dst_type == src_type;
 }
@@ -217,17 +222,18 @@ src1_has_scalar_region(const struct intel_device_info *devinfo,
 }
 
 static unsigned
-num_sources_from_inst(const struct intel_device_info *devinfo,
+num_sources_from_inst(const struct brw_isa_info *isa,
                       const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
    const struct opcode_desc *desc =
-      brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst));
+      brw_opcode_desc(isa, brw_inst_opcode(isa, inst));
    unsigned math_function;
 
-   if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MATH) {
+   if (brw_inst_opcode(isa, inst) == BRW_OPCODE_MATH) {
       math_function = brw_inst_math_function(devinfo, inst);
    } else if (devinfo->ver < 6 &&
-              brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND) {
+              brw_inst_opcode(isa, inst) == BRW_OPCODE_SEND) {
       if (brw_inst_sfid(devinfo, inst) == BRW_SFID_MATH) {
          /* src1 must be a descriptor (including the information to determine
           * that the SEND is doing an extended math operation), but src0 can
@@ -272,9 +278,11 @@ num_sources_from_inst(const struct intel_device_info *devinfo,
 }
 
 static struct string
-invalid_values(const struct intel_device_info *devinfo, const brw_inst *inst)
+invalid_values(const struct brw_isa_info *isa, const brw_inst *inst)
 {
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   const struct intel_device_info *devinfo = isa->devinfo;
+
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    struct string error_msg = { .str = NULL, .len = 0 };
 
    switch ((enum brw_execution_size) brw_inst_exec_size(devinfo, inst)) {
@@ -290,7 +298,7 @@ invalid_values(const struct intel_device_info *devinfo, const brw_inst *inst)
       break;
    }
 
-   if (inst_is_send(devinfo, inst))
+   if (inst_is_send(isa, inst))
       return error_msg;
 
    if (num_sources == 3) {
@@ -342,10 +350,11 @@ invalid_values(const struct intel_device_info *devinfo, const brw_inst *inst)
 }
 
 static struct string
-sources_not_null(const struct intel_device_info *devinfo,
+sources_not_null(const struct brw_isa_info *isa,
                  const brw_inst *inst)
 {
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   const struct intel_device_info *devinfo = isa->devinfo;
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    struct string error_msg = { .str = NULL, .len = 0 };
 
    /* Nothing to test. 3-src instructions can only have GRF sources, and
@@ -357,10 +366,10 @@ sources_not_null(const struct intel_device_info *devinfo,
    /* Nothing to test.  Split sends can only encode a file in sources that are
     * allowed to be NULL.
     */
-   if (inst_is_split_send(devinfo, inst))
+   if (inst_is_split_send(isa, inst))
       return (struct string){};
 
-   if (num_sources >= 1 && brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SYNC)
+   if (num_sources >= 1 && brw_inst_opcode(isa, inst) != BRW_OPCODE_SYNC)
       ERROR_IF(src0_is_null(devinfo, inst), "src0 is null");
 
    if (num_sources == 2)
@@ -370,9 +379,10 @@ sources_not_null(const struct intel_device_info *devinfo,
 }
 
 static struct string
-alignment_supported(const struct intel_device_info *devinfo,
+alignment_supported(const struct brw_isa_info *isa,
                     const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
    struct string error_msg = { .str = NULL, .len = 0 };
 
    ERROR_IF(devinfo->ver >= 11 && brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16,
@@ -382,10 +392,13 @@ alignment_supported(const struct intel_device_info *devinfo,
 }
 
 static bool
-inst_uses_src_acc(const struct intel_device_info *devinfo, const brw_inst *inst)
+inst_uses_src_acc(const struct brw_isa_info *isa,
+                  const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    /* Check instructions that use implicit accumulator sources */
-   switch (brw_inst_opcode(devinfo, inst)) {
+   switch (brw_inst_opcode(isa, inst)) {
    case BRW_OPCODE_MAC:
    case BRW_OPCODE_MACH:
    case BRW_OPCODE_SADA2:
@@ -395,19 +408,21 @@ inst_uses_src_acc(const struct intel_device_info *devinfo, const brw_inst *inst)
    }
 
    /* FIXME: support 3-src instructions */
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    assert(num_sources < 3);
 
    return src0_is_acc(devinfo, inst) || (num_sources > 1 && src1_is_acc(devinfo, inst));
 }
 
 static struct string
-send_restrictions(const struct intel_device_info *devinfo,
+send_restrictions(const struct brw_isa_info *isa,
                   const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    struct string error_msg = { .str = NULL, .len = 0 };
 
-   if (inst_is_split_send(devinfo, inst)) {
+   if (inst_is_split_send(isa, inst)) {
       ERROR_IF(brw_inst_send_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
                brw_inst_send_src1_reg_nr(devinfo, inst) != BRW_ARF_NULL,
                "src1 of split send must be a GRF or NULL");
@@ -441,7 +456,7 @@ send_restrictions(const struct intel_device_info *devinfo,
                    src0_reg_nr < src1_reg_nr + ex_mlen),
                    "split send payloads must not overlap");
       }
-   } else if (inst_is_send(devinfo, inst)) {
+   } else if (inst_is_send(isa, inst)) {
       ERROR_IF(brw_inst_src0_address_mode(devinfo, inst) != BRW_ADDRESS_DIRECT,
                "send must use direct addressing");
 
@@ -469,10 +484,10 @@ send_restrictions(const struct intel_device_info *devinfo,
 }
 
 static bool
-is_unsupported_inst(const struct intel_device_info *devinfo,
+is_unsupported_inst(const struct brw_isa_info *isa,
                     const brw_inst *inst)
 {
-   return brw_inst_opcode(devinfo, inst) == BRW_OPCODE_ILLEGAL;
+   return brw_inst_opcode(isa, inst) == BRW_OPCODE_ILLEGAL;
 }
 
 /**
@@ -522,15 +537,17 @@ execution_type_for_type(enum brw_reg_type type)
  * Returns the execution type of an instruction \p inst
  */
 static enum brw_reg_type
-execution_type(const struct intel_device_info *devinfo, const brw_inst *inst)
+execution_type(const struct brw_isa_info *isa, const brw_inst *inst)
 {
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   const struct intel_device_info *devinfo = isa->devinfo;
+
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    enum brw_reg_type src0_exec_type, src1_exec_type;
 
    /* Execution data type is independent of destination data type, except in
     * mixed F/HF instructions.
     */
-   enum brw_reg_type dst_exec_type = inst_dst_type(devinfo, inst);
+   enum brw_reg_type dst_exec_type = inst_dst_type(isa, inst);
 
    src0_exec_type = execution_type_for_type(brw_inst_src0_type(devinfo, inst));
    if (num_sources == 1) {
@@ -605,12 +622,14 @@ is_packed(unsigned vstride, unsigned width, unsigned hstride)
  * to/from half-float.
  */
 static bool
-is_half_float_conversion(const struct intel_device_info *devinfo,
+is_half_float_conversion(const struct brw_isa_info *isa,
                          const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
 
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
 
    if (dst_type != src0_type &&
@@ -630,21 +649,23 @@ is_half_float_conversion(const struct intel_device_info *devinfo,
  * Returns whether an instruction is using mixed float operation mode
  */
 static bool
-is_mixed_float(const struct intel_device_info *devinfo, const brw_inst *inst)
+is_mixed_float(const struct brw_isa_info *isa, const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    if (devinfo->ver < 8)
       return false;
 
-   if (inst_is_send(devinfo, inst))
+   if (inst_is_send(isa, inst))
       return false;
 
-   unsigned opcode = brw_inst_opcode(devinfo, inst);
-   const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
+   unsigned opcode = brw_inst_opcode(isa, inst);
+   const struct opcode_desc *desc = brw_opcode_desc(isa, opcode);
    if (desc->ndst == 0)
       return false;
 
    /* FIXME: support 3-src instructions */
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    assert(num_sources < 3);
 
    enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
@@ -665,12 +686,14 @@ is_mixed_float(const struct intel_device_info *devinfo, const brw_inst *inst)
  * to/from byte.
  */
 static bool
-is_byte_conversion(const struct intel_device_info *devinfo,
+is_byte_conversion(const struct brw_isa_info *isa,
                    const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst);
 
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
 
    if (dst_type != src0_type &&
@@ -690,16 +713,18 @@ is_byte_conversion(const struct intel_device_info *devinfo,
  * in the "Register Region Restrictions" section.
  */
 static struct string
-general_restrictions_based_on_operand_types(const struct intel_device_info *devinfo,
+general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
                                             const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    const struct opcode_desc *desc =
-      brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst));
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+      brw_opcode_desc(isa, brw_inst_opcode(isa, inst));
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst);
    struct string error_msg = { .str = NULL, .len = 0 };
 
-   if (inst_is_send(devinfo, inst))
+   if (inst_is_send(isa, inst))
       return error_msg;
 
    if (devinfo->ver >= 11) {
@@ -724,7 +749,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
       else
          dst_type = brw_inst_3src_a16_dst_type(devinfo, inst);
    } else {
-      dst_type = inst_dst_type(devinfo, inst);
+      dst_type = inst_dst_type(isa, inst);
    }
 
    ERROR_IF(dst_type == BRW_REGISTER_TYPE_DF &&
@@ -793,18 +818,18 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
 
    unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
    bool dst_type_is_byte =
-      inst_dst_type(devinfo, inst) == BRW_REGISTER_TYPE_B ||
-      inst_dst_type(devinfo, inst) == BRW_REGISTER_TYPE_UB;
+      inst_dst_type(isa, inst) == BRW_REGISTER_TYPE_B ||
+      inst_dst_type(isa, inst) == BRW_REGISTER_TYPE_UB;
 
    if (dst_type_is_byte) {
       if (is_packed(exec_size * dst_stride, exec_size, dst_stride)) {
-         if (!inst_is_raw_move(devinfo, inst))
+         if (!inst_is_raw_move(isa, inst))
             ERROR("Only raw MOV supports a packed-byte destination");
          return error_msg;
       }
    }
 
-   unsigned exec_type = execution_type(devinfo, inst);
+   unsigned exec_type = execution_type(isa, inst);
    unsigned exec_type_size = brw_reg_type_to_size(exec_type);
    unsigned dst_type_size = brw_reg_type_to_size(dst_type);
 
@@ -816,7 +841,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
        exec_type_size == 8 && dst_type_size == 4)
       dst_type_size = 8;
 
-   if (is_byte_conversion(devinfo, inst)) {
+   if (is_byte_conversion(isa, inst)) {
       /* From the BDW+ PRM, Volume 2a, Command Reference, Instructions - MOV:
        *
        *    "There is no direct conversion from B/UB to DF or DF to B/UB.
@@ -841,7 +866,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
                "There are no direct conversions between 64-bit types and B/UB");
    }
 
-   if (is_half_float_conversion(devinfo, inst)) {
+   if (is_half_float_conversion(isa, inst)) {
       /**
        * A helper to validate used in the validation of the following restriction
        * from the BDW+ PRM, Volume 2a, Command Reference, Instructions - MOV:
@@ -917,7 +942,7 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
                     dst_type == BRW_REGISTER_TYPE_HF) {
             unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
             ERROR_IF(dst_stride != 2 &&
-                     !(is_mixed_float(devinfo, inst) &&
+                     !(is_mixed_float(isa, inst) &&
                        dst_stride == 1 && subreg % 16 == 0),
                      "Conversions to HF must have either all words in even "
                      "word locations or all words in odd word locations or "
@@ -931,12 +956,12 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
     * and the execution type. We will add validation for those in a later patch.
     */
    bool validate_dst_size_and_exec_size_ratio =
-      !is_mixed_float(devinfo, inst) ||
+      !is_mixed_float(isa, inst) ||
       !(devinfo->platform == INTEL_PLATFORM_CHV || devinfo->ver >= 9);
 
    if (validate_dst_size_and_exec_size_ratio &&
        exec_type_size > dst_type_size) {
-      if (!(dst_type_is_byte && inst_is_raw_move(devinfo, inst))) {
+      if (!(dst_type_is_byte && inst_is_raw_move(isa, inst))) {
          ERROR_IF(dst_stride * dst_type_size != exec_type_size,
                   "Destination stride must be equal to the ratio of the sizes "
                   "of the execution data type to the destination type");
@@ -973,12 +998,14 @@ general_restrictions_based_on_operand_types(const struct intel_device_info *devi
  * in the "Register Region Restrictions" section.
  */
 static struct string
-general_restrictions_on_region_parameters(const struct intel_device_info *devinfo,
+general_restrictions_on_region_parameters(const struct brw_isa_info *isa,
                                           const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    const struct opcode_desc *desc =
-      brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst));
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+      brw_opcode_desc(isa, brw_inst_opcode(isa, inst));
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst);
    struct string error_msg = { .str = NULL, .len = 0 };
 
@@ -988,7 +1015,7 @@ general_restrictions_on_region_parameters(const struct intel_device_info *devinf
    /* Split sends don't have the bits in the instruction to encode regions so
     * there's nothing to check.
     */
-   if (inst_is_split_send(devinfo, inst))
+   if (inst_is_split_send(isa, inst))
       return (struct string){};
 
    if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16) {
@@ -1132,17 +1159,19 @@ general_restrictions_on_region_parameters(const struct intel_device_info *devinf
 }
 
 static struct string
-special_restrictions_for_mixed_float_mode(const struct intel_device_info *devinfo,
+special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
                                           const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    struct string error_msg = { .str = NULL, .len = 0 };
 
-   const unsigned opcode = brw_inst_opcode(devinfo, inst);
-   const unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   const unsigned opcode = brw_inst_opcode(isa, inst);
+   const unsigned num_sources = num_sources_from_inst(isa, inst);
    if (num_sources >= 3)
       return error_msg;
 
-   if (!is_mixed_float(devinfo, inst))
+   if (!is_mixed_float(isa, inst))
       return error_msg;
 
    unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst);
@@ -1237,7 +1266,7 @@ special_restrictions_for_mixed_float_mode(const struct intel_device_info *devinf
        *
        *    "No accumulator read access for Align16 mixed float."
        */
-      ERROR_IF(inst_uses_src_acc(devinfo, inst),
+      ERROR_IF(inst_uses_src_acc(isa, inst),
                "No accumulator read access for Align16 mixed float");
    } else {
       assert(!is_align16);
@@ -1337,7 +1366,7 @@ special_restrictions_for_mixed_float_mode(const struct intel_device_info *devinf
        *        validate the explicit implication, which is clearly described.
        */
       if (dst_type == BRW_REGISTER_TYPE_HF &&
-          inst_uses_src_acc(devinfo, inst)) {
+          inst_uses_src_acc(isa, inst)) {
          ERROR_IF(dst_stride != 2,
                   "Mixed float mode with implicit/explicit accumulator "
                   "source and half-float destination requires a stride "
@@ -1413,12 +1442,13 @@ registers_read(const uint64_t access_mask[static 32])
  * Region Restrictions" section.
  */
 static struct string
-region_alignment_rules(const struct intel_device_info *devinfo,
+region_alignment_rules(const struct brw_isa_info *isa,
                        const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
    const struct opcode_desc *desc =
-      brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst));
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+      brw_opcode_desc(isa, brw_inst_opcode(isa, inst));
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst);
    uint64_t dst_access_mask[32], src0_access_mask[32], src1_access_mask[32];
    struct string error_msg = { .str = NULL, .len = 0 };
@@ -1429,7 +1459,7 @@ region_alignment_rules(const struct intel_device_info *devinfo,
    if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_16)
       return (struct string){};
 
-   if (inst_is_send(devinfo, inst))
+   if (inst_is_send(isa, inst))
       return (struct string){};
 
    memset(dst_access_mask, 0, sizeof(dst_access_mask));
@@ -1484,7 +1514,7 @@ region_alignment_rules(const struct intel_device_info *devinfo,
       return error_msg;
 
    unsigned stride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
-   enum brw_reg_type dst_type = inst_dst_type(devinfo, inst);
+   enum brw_reg_type dst_type = inst_dst_type(isa, inst);
    unsigned element_size = brw_reg_type_to_size(dst_type);
    unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst);
    unsigned offset = ((exec_size - 1) * stride * element_size) + subreg;
@@ -1570,7 +1600,7 @@ region_alignment_rules(const struct intel_device_info *devinfo,
     * SKL.
     */
    if (devinfo->ver <= 8 ||
-       brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MATH) {
+       brw_inst_opcode(isa, inst) == BRW_OPCODE_MATH) {
 
       /* Nothing explicitly states that on Gen < 8 elements must be evenly
        * split between two destination registers in the two exceptional
@@ -1691,7 +1721,7 @@ region_alignment_rules(const struct intel_device_info *devinfo,
     * is that the size of the destination type is 4 bytes.
     */
    if (devinfo->ver <= 7 && dst_regs == 2) {
-      enum brw_reg_type dst_type = inst_dst_type(devinfo, inst);
+      enum brw_reg_type dst_type = inst_dst_type(isa, inst);
       bool dst_is_packed_dword =
          is_packed(exec_size * stride, exec_size, stride) &&
          brw_reg_type_to_size(dst_type) == 4;
@@ -1727,10 +1757,12 @@ region_alignment_rules(const struct intel_device_info *devinfo,
 }
 
 static struct string
-vector_immediate_restrictions(const struct intel_device_info *devinfo,
+vector_immediate_restrictions(const struct brw_isa_info *isa,
                               const brw_inst *inst)
 {
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   const struct intel_device_info *devinfo = isa->devinfo;
+
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    struct string error_msg = { .str = NULL, .len = 0 };
 
    if (num_sources == 3 || num_sources == 0)
@@ -1742,7 +1774,7 @@ vector_immediate_restrictions(const struct intel_device_info *devinfo,
    if (file != BRW_IMMEDIATE_VALUE)
       return (struct string){};
 
-   enum brw_reg_type dst_type = inst_dst_type(devinfo, inst);
+   enum brw_reg_type dst_type = inst_dst_type(isa, inst);
    unsigned dst_type_size = brw_reg_type_to_size(dst_type);
    unsigned dst_subreg = brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1 ?
                          brw_inst_dst_da1_subreg_nr(devinfo, inst) : 0;
@@ -1789,24 +1821,26 @@ vector_immediate_restrictions(const struct intel_device_info *devinfo,
 
 static struct string
 special_requirements_for_handling_double_precision_data_types(
-                                       const struct intel_device_info *devinfo,
+                                       const struct brw_isa_info *isa,
                                        const brw_inst *inst)
 {
-   unsigned num_sources = num_sources_from_inst(devinfo, inst);
+   const struct intel_device_info *devinfo = isa->devinfo;
+
+   unsigned num_sources = num_sources_from_inst(isa, inst);
    struct string error_msg = { .str = NULL, .len = 0 };
 
    if (num_sources == 3 || num_sources == 0)
       return (struct string){};
 
    /* Split sends don't have types so there's no doubles there. */
-   if (inst_is_split_send(devinfo, inst))
+   if (inst_is_split_send(isa, inst))
       return (struct string){};
 
-   enum brw_reg_type exec_type = execution_type(devinfo, inst);
+   enum brw_reg_type exec_type = execution_type(isa, inst);
    unsigned exec_type_size = brw_reg_type_to_size(exec_type);
 
    enum brw_reg_file dst_file = brw_inst_dst_reg_file(devinfo, inst);
-   enum brw_reg_type dst_type = inst_dst_type(devinfo, inst);
+   enum brw_reg_type dst_type = inst_dst_type(isa, inst);
    unsigned dst_type_size = brw_reg_type_to_size(dst_type);
    unsigned dst_hstride = STRIDE(brw_inst_dst_hstride(devinfo, inst));
    unsigned dst_reg = brw_inst_dst_da_reg_nr(devinfo, inst);
@@ -1815,7 +1849,7 @@ special_requirements_for_handling_double_precision_data_types(
 
    bool is_integer_dword_multiply =
       devinfo->ver >= 8 &&
-      brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MUL &&
+      brw_inst_opcode(isa, inst) == BRW_OPCODE_MUL &&
       (brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_D ||
        brw_inst_src0_type(devinfo, inst) == BRW_REGISTER_TYPE_UD) &&
       (brw_inst_src1_type(devinfo, inst) == BRW_REGISTER_TYPE_D ||
@@ -1915,7 +1949,7 @@ special_requirements_for_handling_double_precision_data_types(
       if (is_double_precision &&
           (devinfo->platform == INTEL_PLATFORM_CHV ||
            intel_device_info_is_9lp(devinfo))) {
-         ERROR_IF(brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MAC ||
+         ERROR_IF(brw_inst_opcode(isa, inst) == BRW_OPCODE_MAC ||
                   brw_inst_acc_wr_control(devinfo, inst) ||
                   (BRW_ARCHITECTURE_REGISTER_FILE == file &&
                    reg != BRW_ARF_NULL) ||
@@ -2011,9 +2045,10 @@ special_requirements_for_handling_double_precision_data_types(
 }
 
 static struct string
-instruction_restrictions(const struct intel_device_info *devinfo,
+instruction_restrictions(const struct brw_isa_info *isa,
                          const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
    struct string error_msg = { .str = NULL, .len = 0 };
 
    /* From Wa_1604601757:
@@ -2022,8 +2057,8 @@ instruction_restrictions(const struct intel_device_info *devinfo,
     *  is not supported."
     */
    if (devinfo->ver >= 12 &&
-       brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MUL) {
-      enum brw_reg_type exec_type = execution_type(devinfo, inst);
+       brw_inst_opcode(isa, inst) == BRW_OPCODE_MUL) {
+      enum brw_reg_type exec_type = execution_type(isa, inst);
       const bool src0_valid = type_sz(brw_inst_src0_type(devinfo, inst)) == 4 ||
          brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE ||
          !(brw_inst_src0_negate(devinfo, inst) ||
@@ -2039,8 +2074,8 @@ instruction_restrictions(const struct intel_device_info *devinfo,
                "modifier is not supported.");
    }
 
-   if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_CMP ||
-       brw_inst_opcode(devinfo, inst) == BRW_OPCODE_CMPN) {
+   if (brw_inst_opcode(isa, inst) == BRW_OPCODE_CMP ||
+       brw_inst_opcode(isa, inst) == BRW_OPCODE_CMPN) {
       if (devinfo->ver <= 7) {
          /* Page 166 of the Ivy Bridge PRM Volume 4 part 3 (Execution Unit
           * ISA) says:
@@ -2077,7 +2112,7 @@ instruction_restrictions(const struct intel_device_info *devinfo,
       }
    }
 
-   if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MATH) {
+   if (brw_inst_opcode(isa, inst) == BRW_OPCODE_MATH) {
       unsigned math_function = brw_inst_math_function(devinfo, inst);
       switch (math_function) {
       case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
@@ -2100,7 +2135,7 @@ instruction_restrictions(const struct intel_device_info *devinfo,
       }
    }
 
-   if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DP4A) {
+   if (brw_inst_opcode(isa, inst) == BRW_OPCODE_DP4A) {
       /* Page 396 (page 412 of the PDF) of the DG1 PRM volume 2a says:
        *
        *    Only one of src0 or src1 operand may be an the (sic) accumulator
@@ -2116,16 +2151,17 @@ instruction_restrictions(const struct intel_device_info *devinfo,
 }
 
 static struct string
-send_descriptor_restrictions(const struct intel_device_info *devinfo,
+send_descriptor_restrictions(const struct brw_isa_info *isa,
                              const brw_inst *inst)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
    struct string error_msg = { .str = NULL, .len = 0 };
 
-   if (inst_is_split_send(devinfo, inst)) {
+   if (inst_is_split_send(isa, inst)) {
       /* We can only validate immediate descriptors */
       if (brw_inst_send_sel_reg32_desc(devinfo, inst))
          return error_msg;
-   } else if (inst_is_send(devinfo, inst)) {
+   } else if (inst_is_send(isa, inst)) {
       /* We can only validate immediate descriptors */
       if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE)
          return error_msg;
@@ -2155,13 +2191,13 @@ send_descriptor_restrictions(const struct intel_device_info *devinfo,
 }
 
 bool
-brw_validate_instruction(const struct intel_device_info *devinfo,
+brw_validate_instruction(const struct brw_isa_info *isa,
                          const brw_inst *inst, int offset,
                          struct disasm_info *disasm)
 {
    struct string error_msg = { .str = NULL, .len = 0 };
 
-   if (is_unsupported_inst(devinfo, inst)) {
+   if (is_unsupported_inst(isa, inst)) {
       ERROR("Instruction not supported on this Gen");
    } else {
       CHECK(invalid_values);
@@ -2190,10 +2226,11 @@ brw_validate_instruction(const struct intel_device_info *devinfo,
 }
 
 bool
-brw_validate_instructions(const struct intel_device_info *devinfo,
+brw_validate_instructions(const struct brw_isa_info *isa,
                           const void *assembly, int start_offset, int end_offset,
                           struct disasm_info *disasm)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
    bool valid = true;
 
    for (int src_offset = start_offset; src_offset < end_offset;) {
@@ -2205,11 +2242,11 @@ brw_validate_instructions(const struct intel_device_info *devinfo,
 
       if (is_compact) {
          brw_compact_inst *compacted = (void *)inst;
-         brw_uncompact_instruction(devinfo, &uncompacted, compacted);
+         brw_uncompact_instruction(isa, &uncompacted, compacted);
          inst = &uncompacted;
       }
 
-      bool v = brw_validate_instruction(devinfo, inst, src_offset, disasm);
+      bool v = brw_validate_instruction(isa, inst, src_offset, disasm);
       valid = valid && v;
 
       src_offset += inst_size;
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index ddb72c54b9a..19885438115 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -45,7 +45,7 @@
 
 using namespace brw;
 
-static unsigned get_lowered_simd_width(const struct intel_device_info *devinfo,
+static unsigned get_lowered_simd_width(const struct brw_compiler *compiler,
                                        const fs_inst *inst);
 
 void
@@ -4064,7 +4064,7 @@ fs_visitor::lower_mulh_inst(fs_inst *inst, bblock_t *block)
       lower_src_modifiers(this, block, inst, 1);
 
    /* Should have been lowered to 8-wide. */
-   assert(inst->exec_size <= get_lowered_simd_width(devinfo, inst));
+   assert(inst->exec_size <= get_lowered_simd_width(compiler, inst));
    const fs_reg acc = retype(brw_acc_reg(inst->exec_size), inst->dst.type);
    fs_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]);
    fs_inst *mach = ibld.MACH(inst->dst, inst->src[0], inst->src[1]);
@@ -7072,9 +7072,11 @@ is_mixed_float_with_packed_fp16_dst(const fs_inst *inst)
  * excessively restrictive.
  */
 static unsigned
-get_fpu_lowered_simd_width(const struct intel_device_info *devinfo,
+get_fpu_lowered_simd_width(const struct brw_compiler *compiler,
                            const fs_inst *inst)
 {
+   const struct intel_device_info *devinfo = compiler->devinfo;
+
    /* Maximum execution size representable in the instruction controls. */
    unsigned max_width = MIN2(32, inst->exec_size);
 
@@ -7173,7 +7175,7 @@ get_fpu_lowered_simd_width(const struct intel_device_info *devinfo,
     * From the BDW PRMs (applies to later hardware too):
     *  "Ternary instruction with condition modifiers must not use SIMD32."
     */
-   if (inst->conditional_mod && (devinfo->ver < 8 || inst->is_3src(devinfo)))
+   if (inst->conditional_mod && (devinfo->ver < 8 || inst->is_3src(compiler)))
       max_width = MIN2(max_width, 16);
 
    /* From the IVB PRMs (applies to other devices that don't have the
@@ -7181,7 +7183,7 @@ get_fpu_lowered_simd_width(const struct intel_device_info *devinfo,
     *  "In Align16 access mode, SIMD16 is not allowed for DW operations and
     *   SIMD8 is not allowed for DF operations."
     */
-   if (inst->is_3src(devinfo) && !devinfo->supports_simd16_3src)
+   if (inst->is_3src(compiler) && !devinfo->supports_simd16_3src)
       max_width = MIN2(max_width, inst->exec_size / reg_count);
 
    /* Pre-Gfx8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
@@ -7330,9 +7332,11 @@ get_sampler_lowered_simd_width(const struct intel_device_info *devinfo,
  * original execution size.
  */
 static unsigned
-get_lowered_simd_width(const struct intel_device_info *devinfo,
+get_lowered_simd_width(const struct brw_compiler *compiler,
                        const fs_inst *inst)
 {
+   const struct intel_device_info *devinfo = compiler->devinfo;
+
    switch (inst->opcode) {
    case BRW_OPCODE_MOV:
    case BRW_OPCODE_SEL:
@@ -7371,7 +7375,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
    case SHADER_OPCODE_SEL_EXEC:
    case SHADER_OPCODE_CLUSTER_BROADCAST:
    case SHADER_OPCODE_MOV_RELOC_IMM:
-      return get_fpu_lowered_simd_width(devinfo, inst);
+      return get_fpu_lowered_simd_width(compiler, inst);
 
    case BRW_OPCODE_CMP: {
       /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
@@ -7387,7 +7391,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
        */
       const unsigned max_width = (devinfo->verx10 == 70 &&
                                   !inst->dst.is_null() ? 8 : ~0);
-      return MIN2(max_width, get_fpu_lowered_simd_width(devinfo, inst));
+      return MIN2(max_width, get_fpu_lowered_simd_width(compiler, inst));
    }
    case BRW_OPCODE_BFI1:
    case BRW_OPCODE_BFI2:
@@ -7396,7 +7400,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
        *  "Force BFI instructions to be executed always in SIMD8."
        */
       return MIN2(devinfo->platform == INTEL_PLATFORM_HSW ? 8 : ~0u,
-                  get_fpu_lowered_simd_width(devinfo, inst));
+                  get_fpu_lowered_simd_width(compiler, inst));
 
    case BRW_OPCODE_IF:
       assert(inst->src[0].file == BAD_FILE || inst->exec_size <= 16);
@@ -7432,7 +7436,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
 
    case SHADER_OPCODE_USUB_SAT:
    case SHADER_OPCODE_ISUB_SAT:
-      return get_fpu_lowered_simd_width(devinfo, inst);
+      return get_fpu_lowered_simd_width(compiler, inst);
 
    case SHADER_OPCODE_INT_QUOTIENT:
    case SHADER_OPCODE_INT_REMAINDER:
@@ -7494,7 +7498,7 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
        * is 8-wide on Gfx7+.
        */
       return (devinfo->ver >= 7 ? 8 :
-              get_fpu_lowered_simd_width(devinfo, inst));
+              get_fpu_lowered_simd_width(compiler, inst));
 
    case FS_OPCODE_FB_WRITE_LOGICAL:
       /* Gfx6 doesn't support SIMD16 depth writes but we cannot handle them
@@ -7597,10 +7601,10 @@ get_lowered_simd_width(const struct intel_device_info *devinfo,
    case SHADER_OPCODE_QUAD_SWIZZLE: {
       const unsigned swiz = inst->src[1].ud;
       return (is_uniform(inst->src[0]) ?
-                 get_fpu_lowered_simd_width(devinfo, inst) :
+                 get_fpu_lowered_simd_width(compiler, inst) :
               devinfo->ver < 11 && type_sz(inst->src[0].type) == 4 ? 8 :
               swiz == BRW_SWIZZLE_XYXY || swiz == BRW_SWIZZLE_ZWZW ? 4 :
-              get_fpu_lowered_simd_width(devinfo, inst));
+              get_fpu_lowered_simd_width(compiler, inst));
    }
    case SHADER_OPCODE_MOV_INDIRECT: {
       /* From IVB and HSW PRMs:
@@ -7810,7 +7814,7 @@ fs_visitor::lower_simd_width()
    bool progress = false;
 
    foreach_block_and_inst_safe(block, fs_inst, inst, cfg) {
-      const unsigned lower_width = get_lowered_simd_width(devinfo, inst);
+      const unsigned lower_width = get_lowered_simd_width(compiler, inst);
 
       if (lower_width != inst->exec_size) {
          /* Builder matching the original instruction.  We may also need to
@@ -8113,7 +8117,7 @@ fs_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) con
               inst->flag_subreg % 2);
    }
 
-   fprintf(file, "%s", brw_instruction_name(devinfo, inst->opcode));
+   fprintf(file, "%s", brw_instruction_name(&compiler->isa, inst->opcode));
    if (inst->saturate)
       fprintf(file, ".sat");
    if (inst->conditional_mod) {
@@ -8707,7 +8711,7 @@ fs_visitor::fixup_3src_null_dest()
    bool progress = false;
 
    foreach_block_and_inst_safe (block, fs_inst, inst, cfg) {
-      if (inst->is_3src(devinfo) && inst->dst.is_null()) {
+      if (inst->is_3src(compiler) && inst->dst.is_null()) {
          inst->dst = fs_reg(VGRF, alloc.allocate(dispatch_width / 8),
                             inst->dst.type);
          progress = true;
diff --git a/src/intel/compiler/brw_fs_bank_conflicts.cpp b/src/intel/compiler/brw_fs_bank_conflicts.cpp
index ec8d699d7db..a390a615752 100644
--- a/src/intel/compiler/brw_fs_bank_conflicts.cpp
+++ b/src/intel/compiler/brw_fs_bank_conflicts.cpp
@@ -645,7 +645,7 @@ namespace {
          } else if (inst->opcode == BRW_OPCODE_WHILE) {
             block_scale /= 10;
 
-         } else if (inst->is_3src(v->devinfo) &&
+         } else if (inst->is_3src(v->compiler) &&
                     is_grf(inst->src[1]) && is_grf(inst->src[2])) {
             const unsigned r = p.atom_of_reg(reg_of(inst->src[1]));
             const unsigned s = p.atom_of_reg(reg_of(inst->src[2]));
@@ -942,10 +942,10 @@ fs_visitor::opt_bank_conflicts()
  * we don't know which bank each VGRF is going to end up aligned to.
  */
 bool
-has_bank_conflict(const intel_device_info *devinfo, const fs_inst *inst)
+has_bank_conflict(const struct brw_isa_info *isa, const fs_inst *inst)
 {
-   return inst->is_3src(devinfo) &&
+   return is_3src(isa, inst->opcode) &&
           is_grf(inst->src[1]) && is_grf(inst->src[2]) &&
           bank_of(reg_of(inst->src[1])) == bank_of(reg_of(inst->src[2])) &&
-          !is_conflict_optimized_out(devinfo, inst);
+          !is_conflict_optimized_out(isa->devinfo, inst);
 }
diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp
index dd7dc16dc4f..fd3dfc157fa 100644
--- a/src/intel/compiler/brw_fs_copy_propagation.cpp
+++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
@@ -370,8 +370,10 @@ is_logic_op(enum opcode opcode)
 static bool
 can_take_stride(fs_inst *inst, brw_reg_type dst_type,
                 unsigned arg, unsigned stride,
-                const intel_device_info *devinfo)
+                const struct brw_compiler *compiler)
 {
+   const struct intel_device_info *devinfo = compiler->devinfo;
+
    if (stride > 4)
       return false;
 
@@ -395,7 +397,7 @@ can_take_stride(fs_inst *inst, brw_reg_type dst_type,
     *    This is applicable to 32b datatypes and 16b datatype. 64b datatypes
     *    cannot use the replicate control.
     */
-   if (inst->is_3src(devinfo)) {
+   if (inst->is_3src(compiler)) {
       if (type_sz(inst->src[arg].type) > 4)
          return stride == 1;
       else
@@ -545,7 +547,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
     */
    if (!can_take_stride(inst, dst_type, arg,
                         entry_stride * inst->src[arg].stride,
-                        devinfo))
+                        compiler))
       return false;
 
    /* From the Cherry Trail/Braswell PRMs, Volume 7: 3D Media GPGPU:
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index a9032e4c0a9..11f831fdbcd 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -197,7 +197,7 @@ fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
      shader_name(NULL), stage(stage), mem_ctx(mem_ctx)
 {
    p = rzalloc(mem_ctx, struct brw_codegen);
-   brw_init_codegen(devinfo, p, mem_ctx);
+   brw_init_codegen(&compiler->isa, p, mem_ctx);
 
    /* In the FS code generator, we are very careful to ensure that we always
     * set the right execution size so we don't need the EU code to "help" us
@@ -252,7 +252,7 @@ fs_generator::patch_halt_jumps()
    foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
       brw_inst *patch = &p->store[patch_ip->ip];
 
-      assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
+      assert(brw_inst_opcode(p->isa, patch) == BRW_OPCODE_HALT);
       if (devinfo->ver >= 6) {
          /* HALT takes a half-instruction distance from the pre-incremented IP. */
          brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
@@ -343,13 +343,13 @@ fs_generator::generate_send(fs_inst *inst,
                                       desc, desc_imm, ex_desc, ex_desc_imm,
                                       inst->eot);
       if (inst->check_tdr)
-         brw_inst_set_opcode(p->devinfo, brw_last_inst,
+         brw_inst_set_opcode(p->isa, brw_last_inst,
                              devinfo->ver >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
    } else {
       brw_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm,
                                    inst->eot);
       if (inst->check_tdr)
-         brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
+         brw_inst_set_opcode(p->isa, brw_last_inst, BRW_OPCODE_SENDC);
    }
 }
 
@@ -1831,7 +1831,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
    int loop_count = 0, send_count = 0, nop_count = 0;
    bool is_accum_used = false;
 
-   struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
+   struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg);
 
    foreach_block_and_inst (block, fs_inst, inst, cfg) {
       if (inst->opcode == SHADER_OPCODE_UNDEF)
@@ -1854,7 +1854,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
       if (devinfo->ver >= 8 &&
           devinfo->ver <= 9 &&
           p->nr_insn > 1 &&
-          brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
+          brw_inst_opcode(p->isa, brw_last_inst) == BRW_OPCODE_MATH &&
           brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
           inst->dst.component_size(inst->exec_size) > REG_SIZE) {
          brw_NOP(p);
@@ -2637,7 +2637,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
 #else
    if (unlikely(debug_flag))
 #endif
-      brw_validate_instructions(devinfo, p->store,
+      brw_validate_instructions(&compiler->isa, p->store,
                                 start_offset,
                                 p->next_insn_offset,
                                 disasm_info);
diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h
index 0e5cee7c42e..02acd6aa70f 100644
--- a/src/intel/compiler/brw_inst.h
+++ b/src/intel/compiler/brw_inst.h
@@ -1446,17 +1446,17 @@ FC(3src_hw_opcode,      /* 4+ */  6,  0, /* 12+ */  6,  0, devinfo->ver >= 8)
 #undef F
 
 static inline void
-brw_inst_set_opcode(const struct intel_device_info *devinfo,
+brw_inst_set_opcode(const struct brw_isa_info *isa,
                     struct brw_inst *inst, enum opcode opcode)
 {
-   brw_inst_set_hw_opcode(devinfo, inst, brw_opcode_encode(devinfo, opcode));
+   brw_inst_set_hw_opcode(isa->devinfo, inst, brw_opcode_encode(isa, opcode));
 }
 
 static inline enum opcode
-brw_inst_opcode(const struct intel_device_info *devinfo,
+brw_inst_opcode(const struct brw_isa_info *isa,
                 const struct brw_inst *inst)
 {
-   return brw_opcode_decode(devinfo, brw_inst_hw_opcode(devinfo, inst));
+   return brw_opcode_decode(isa, brw_inst_hw_opcode(isa->devinfo, inst));
 }
 
 #ifdef __cplusplus
diff --git a/src/intel/compiler/brw_ir.h b/src/intel/compiler/brw_ir.h
index a8e899359e9..8db0c988ceb 100644
--- a/src/intel/compiler/brw_ir.h
+++ b/src/intel/compiler/brw_ir.h
@@ -90,7 +90,7 @@ struct backend_reg : private brw_reg
 struct bblock_t;
 
 struct backend_instruction : public exec_node {
-   bool is_3src(const struct intel_device_info *devinfo) const;
+   bool is_3src(const struct brw_compiler *compiler) const;
    bool is_tex() const;
    bool is_math() const;
    bool is_control_flow() const;
diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
index 6f7bab25272..063f183b0f3 100644
--- a/src/intel/compiler/brw_ir_fs.h
+++ b/src/intel/compiler/brw_ir_fs.h
@@ -688,6 +688,6 @@ is_coalescing_payload(const brw::simple_allocator &alloc, const fs_inst *inst)
 }
 
 bool
-has_bank_conflict(const intel_device_info *devinfo, const fs_inst *inst);
+has_bank_conflict(const struct brw_isa_info *isa, const fs_inst *inst);
 
 #endif
diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp
index e05a6b8fa42..2ed4e7ca2cc 100644
--- a/src/intel/compiler/brw_ir_performance.cpp
+++ b/src/intel/compiler/brw_ir_performance.cpp
@@ -120,11 +120,11 @@ namespace {
     * instructions.
     */
    struct instruction_info {
-      instruction_info(const intel_device_info *devinfo, const fs_inst *inst) :
-         devinfo(devinfo), op(inst->opcode),
+      instruction_info(const struct brw_isa_info *isa, const fs_inst *inst) :
+         isa(isa), devinfo(isa->devinfo), op(inst->opcode),
          td(inst->dst.type), sd(DIV_ROUND_UP(inst->size_written, REG_SIZE)),
          tx(get_exec_type(inst)), sx(0), ss(0),
-         sc(has_bank_conflict(devinfo, inst) ? sd : 0),
+         sc(has_bank_conflict(isa, inst) ? sd : 0),
          desc(inst->desc), sfid(inst->sfid)
       {
          /* We typically want the maximum source size, except for split send
@@ -150,9 +150,9 @@ namespace {
             tx = brw_int_type(8, tx == BRW_REGISTER_TYPE_D);
       }
 
-      instruction_info(const intel_device_info *devinfo,
+      instruction_info(const struct brw_isa_info *isa,
                        const vec4_instruction *inst) :
-         devinfo(devinfo), op(inst->opcode),
+         isa(isa), devinfo(isa->devinfo), op(inst->opcode),
          td(inst->dst.type), sd(DIV_ROUND_UP(inst->size_written, REG_SIZE)),
          tx(get_exec_type(inst)), sx(0), ss(0), sc(0),
          desc(inst->desc), sfid(inst->sfid)
@@ -173,6 +173,8 @@ namespace {
             tx = brw_int_type(8, tx == BRW_REGISTER_TYPE_D);
       }
 
+      /** ISA encoding information */
+      const struct brw_isa_info *isa;
       /** Device information. */
       const struct intel_device_info *devinfo;
       /** Instruction opcode. */
@@ -1338,11 +1340,12 @@ namespace {
     * Model the performance behavior of an FS back-end instruction.
     */
    void
-   issue_fs_inst(state &st, const intel_device_info *devinfo,
+   issue_fs_inst(state &st, const struct brw_isa_info *isa,
                  const backend_instruction *be_inst)
    {
+      const struct intel_device_info *devinfo = isa->devinfo;
       const fs_inst *inst = static_cast<const fs_inst *>(be_inst);
-      const instruction_info info(devinfo, inst);
+      const instruction_info info(isa, inst);
       const perf_desc perf = instruction_desc(info);
 
       /* Stall on any source dependencies. */
@@ -1458,12 +1461,13 @@ namespace {
     * Model the performance behavior of a VEC4 back-end instruction.
     */
    void
-   issue_vec4_instruction(state &st, const intel_device_info *devinfo,
+   issue_vec4_instruction(state &st, const struct brw_isa_info *isa,
                           const backend_instruction *be_inst)
    {
+      const struct intel_device_info *devinfo = isa->devinfo;
       const vec4_instruction *inst =
          static_cast<const vec4_instruction *>(be_inst);
-      const instruction_info info(devinfo, inst);
+      const instruction_info info(isa, inst);
       const perf_desc perf = instruction_desc(info);
 
       /* Stall on any source dependencies. */
@@ -1569,7 +1573,7 @@ namespace {
    void
    calculate_performance(performance &p, const backend_shader *s,
                          void (*issue_instruction)(
-                            state &, const intel_device_info *,
+                            state &, const struct brw_isa_info *,
                             const backend_instruction *),
                          unsigned dispatch_width)
    {
@@ -1611,7 +1615,7 @@ namespace {
          foreach_inst_in_block(backend_instruction, inst, block) {
             const unsigned clock0 = st.unit_ready[EU_UNIT_FE];
 
-            issue_instruction(st, s->devinfo, inst);
+            issue_instruction(st, &s->compiler->isa, inst);
 
             if (inst->opcode == SHADER_OPCODE_HALT_TARGET && halt_count)
                st.weight /= discard_weight;
diff --git a/src/intel/compiler/brw_isa_info.h b/src/intel/compiler/brw_isa_info.h
index f04ceab40ad..615fd2d086a 100644
--- a/src/intel/compiler/brw_isa_info.h
+++ b/src/intel/compiler/brw_isa_info.h
@@ -30,6 +30,15 @@
 extern "C" {
 #endif
 
+struct opcode_desc;
+
+struct brw_isa_info {
+   const struct intel_device_info *devinfo;
+};
+
+void brw_init_isa_info(struct brw_isa_info *isa,
+                       const struct intel_device_info *devinfo);
+
 struct opcode_desc {
    unsigned ir;
    unsigned hw;
@@ -40,28 +49,28 @@ struct opcode_desc {
 };
 
 const struct opcode_desc *
-brw_opcode_desc(const struct intel_device_info *devinfo, enum opcode opcode);
+brw_opcode_desc(const struct brw_isa_info *isa, enum opcode opcode);
 
 const struct opcode_desc *
-brw_opcode_desc_from_hw(const struct intel_device_info *devinfo, unsigned hw);
+brw_opcode_desc_from_hw(const struct brw_isa_info *isa, unsigned hw);
 
 static inline unsigned
-brw_opcode_encode(const struct intel_device_info *devinfo, enum opcode opcode)
+brw_opcode_encode(const struct brw_isa_info *isa, enum opcode opcode)
 {
-   return brw_opcode_desc(devinfo, opcode)->hw;
+   return brw_opcode_desc(isa, opcode)->hw;
 }
 
 static inline enum opcode
-brw_opcode_decode(const struct intel_device_info *devinfo, unsigned hw)
+brw_opcode_decode(const struct brw_isa_info *isa, unsigned hw)
 {
-   const struct opcode_desc *desc = brw_opcode_desc_from_hw(devinfo, hw);
+   const struct opcode_desc *desc = brw_opcode_desc_from_hw(isa, hw);
    return desc ? (enum opcode)desc->ir : BRW_OPCODE_ILLEGAL;
 }
 
 static inline bool
-is_3src(const struct intel_device_info *devinfo, enum opcode opcode)
+is_3src(const struct brw_isa_info *isa, enum opcode opcode)
 {
-   const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
+   const struct opcode_desc *desc = brw_opcode_desc(isa, opcode);
    return desc && desc->nsrc == 3;
 }
 
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
index 5efea03e04a..5ae93827d31 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -67,7 +67,7 @@ public:
    void set_latency_gfx4();
    void set_latency_gfx7(bool is_haswell);
 
-   const struct intel_device_info *devinfo;
+   const struct brw_isa_info *isa;
    backend_instruction *inst;
    schedule_node **children;
    int *child_latency;
@@ -400,7 +400,7 @@ schedule_node::set_latency_gfx7(bool is_haswell)
       }
 
       case GFX6_SFID_DATAPORT_RENDER_CACHE:
-         switch (brw_fb_desc_msg_type(devinfo, inst->desc)) {
+         switch (brw_fb_desc_msg_type(isa->devinfo, inst->desc)) {
          case GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE:
          case GFX7_DATAPORT_RC_TYPED_SURFACE_READ:
             /* See also SHADER_OPCODE_TYPED_SURFACE_READ */
@@ -531,7 +531,7 @@ schedule_node::set_latency_gfx7(bool is_haswell)
       case GFX12_SFID_UGM:
       case GFX12_SFID_TGM:
       case GFX12_SFID_SLM:
-         switch (lsc_msg_desc_opcode(devinfo, inst->desc)) {
+         switch (lsc_msg_desc_opcode(isa->devinfo, inst->desc)) {
          case LSC_OP_LOAD:
          case LSC_OP_STORE:
          case LSC_OP_LOAD_CMASK:
@@ -957,7 +957,7 @@ schedule_node::schedule_node(backend_instruction *inst,
 {
    const struct intel_device_info *devinfo = sched->bs->devinfo;
 
-   this->devinfo = devinfo;
+   this->isa = &sched->bs->compiler->isa;
    this->inst = inst;
    this->child_array_size = 0;
    this->children = NULL;
@@ -1727,8 +1727,9 @@ vec4_instruction_scheduler::choose_instruction_to_schedule()
 int
 fs_instruction_scheduler::issue_time(backend_instruction *inst0)
 {
+   const struct brw_isa_info *isa = &v->compiler->isa;
    const fs_inst *inst = static_cast<fs_inst *>(inst0);
-   const unsigned overhead = v->grf_used && has_bank_conflict(v->devinfo, inst) ?
+   const unsigned overhead = v->grf_used && has_bank_conflict(isa, inst) ?
       DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE) : 0;
    if (is_compressed(inst))
       return 4 + overhead;
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 6efb819f137..db221ac11d3 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -162,8 +162,10 @@ brw_texture_offset(const nir_tex_instr *tex, unsigned src,
 }
 
 const char *
-brw_instruction_name(const struct intel_device_info *devinfo, enum opcode op)
+brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    switch (op) {
    case 0 ... NUM_BRW_OPCODES - 1:
       /* The DO instruction doesn't exist on Gfx6+, but we use it to mark the
@@ -181,8 +183,8 @@ brw_instruction_name(const struct intel_device_info *devinfo, enum opcode op)
       if (devinfo->ver > 7 && op == BRW_OPCODE_F16TO32)
          return "f16to32";
 
-      assert(brw_opcode_desc(devinfo, op)->name);
-      return brw_opcode_desc(devinfo, op)->name;
+      assert(brw_opcode_desc(isa, op)->name);
+      return brw_opcode_desc(isa, op)->name;
    case FS_OPCODE_FB_WRITE:
       return "fb_write";
    case FS_OPCODE_FB_WRITE_LOGICAL:
@@ -887,9 +889,9 @@ backend_instruction::is_commutative() const
 }
 
 bool
-backend_instruction::is_3src(const struct intel_device_info *devinfo) const
+backend_instruction::is_3src(const struct brw_compiler *compiler) const
 {
-   return ::is_3src(devinfo, opcode);
+   return ::is_3src(&compiler->isa, opcode);
 }
 
 bool
diff --git a/src/intel/compiler/brw_shader.h b/src/intel/compiler/brw_shader.h
index dc201a66a3e..cea8c0f3e9e 100644
--- a/src/intel/compiler/brw_shader.h
+++ b/src/intel/compiler/brw_shader.h
@@ -99,7 +99,7 @@ struct backend_shader;
 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 uint32_t brw_math_function(enum opcode op);
-const char *brw_instruction_name(const struct intel_device_info *devinfo,
+const char *brw_instruction_name(const struct brw_isa_info *isa,
                                  enum opcode op);
 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 96978dbb317..81641db2593 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -1321,7 +1321,7 @@ vec4_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) c
               pred_ctrl_align16[inst->predicate]);
    }
 
-   fprintf(file, "%s(%d)", brw_instruction_name(devinfo, inst->opcode),
+   fprintf(file, "%s(%d)", brw_instruction_name(&compiler->isa, inst->opcode),
            inst->exec_size);
    if (inst->saturate)
       fprintf(file, ".sat");
@@ -1697,7 +1697,7 @@ vec4_visitor::fixup_3src_null_dest()
    bool progress = false;
 
    foreach_block_and_inst_safe (block, vec4_instruction, inst, cfg) {
-      if (inst->is_3src(devinfo) && inst->dst.is_null()) {
+      if (inst->is_3src(compiler) && inst->dst.is_null()) {
          const unsigned size_written = type_sz(inst->dst.type);
          const unsigned num_regs = DIV_ROUND_UP(size_written, REG_SIZE);
 
@@ -1790,7 +1790,7 @@ vec4_visitor::convert_to_hw_regs()
             src.vstride = src.width + src.hstride;
       }
 
-      if (inst->is_3src(devinfo)) {
+      if (inst->is_3src(compiler)) {
          /* 3-src instructions with scalar sources support arbitrary subnr,
           * but don't actually use swizzles.  Convert swizzle into subnr.
           * Skip this for double-precision instructions: RepCtrl=1 is not
diff --git a/src/intel/compiler/brw_vec4_copy_propagation.cpp b/src/intel/compiler/brw_vec4_copy_propagation.cpp
index 717a7186b2c..21be3a6b67a 100644
--- a/src/intel/compiler/brw_vec4_copy_propagation.cpp
+++ b/src/intel/compiler/brw_vec4_copy_propagation.cpp
@@ -299,10 +299,12 @@ is_align1_opcode(unsigned opcode)
 }
 
 static bool
-try_copy_propagate(const struct intel_device_info *devinfo,
+try_copy_propagate(const struct brw_compiler *compiler,
                    vec4_instruction *inst, int arg,
                    const copy_entry *entry, int attributes_per_reg)
 {
+   const struct intel_device_info *devinfo = compiler->devinfo;
+
    /* Build up the value we are propagating as if it were the source of a
     * single MOV
     */
@@ -380,7 +382,7 @@ try_copy_propagate(const struct intel_device_info *devinfo,
    if (is_align1_opcode(inst->opcode) && composed_swizzle != BRW_SWIZZLE_XYZW)
       return false;
 
-   if (inst->is_3src(devinfo) &&
+   if (inst->is_3src(compiler) &&
        (value.file == UNIFORM ||
         (value.file == ATTR && attributes_per_reg != 1)) &&
        !brw_is_single_value_swizzle(composed_swizzle))
@@ -503,7 +505,7 @@ vec4_visitor::opt_copy_propagation(bool do_constant_prop)
 
          if (do_constant_prop && try_constant_propagate(inst, i, &entry))
             progress = true;
-         else if (try_copy_propagate(devinfo, inst, i, &entry, attributes_per_reg))
+         else if (try_copy_propagate(compiler, inst, i, &entry, attributes_per_reg))
 	    progress = true;
       }
 
diff --git a/src/intel/compiler/brw_vec4_generator.cpp b/src/intel/compiler/brw_vec4_generator.cpp
index 965216020fa..4b9600f4de2 100644
--- a/src/intel/compiler/brw_vec4_generator.cpp
+++ b/src/intel/compiler/brw_vec4_generator.cpp
@@ -1523,7 +1523,7 @@ generate_code(struct brw_codegen *p,
 {
    const struct intel_device_info *devinfo = p->devinfo;
    const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->info.stage);
-   struct disasm_info *disasm_info = disasm_initialize(devinfo, cfg);
+   struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg);
 
    /* `send_count` explicitly does not include spills or fills, as we'd
     * like to use it as a metric for intentional memory access or other
@@ -2216,7 +2216,7 @@ generate_code(struct brw_codegen *p,
 #else
    if (unlikely(debug_enabled))
 #endif
-      brw_validate_instructions(devinfo, p->store,
+      brw_validate_instructions(&compiler->isa, p->store,
                                 0, p->next_insn_offset,
                                 disasm_info);
 
@@ -2283,7 +2283,7 @@ brw_vec4_generate_assembly(const struct brw_compiler *compiler,
                            bool debug_enabled)
 {
    struct brw_codegen *p = rzalloc(mem_ctx, struct brw_codegen);
-   brw_init_codegen(compiler->devinfo, p, mem_ctx);
+   brw_init_codegen(&compiler->isa, p, mem_ctx);
    brw_set_default_access_mode(p, BRW_ALIGN_16);
 
    generate_code(p, compiler, log_data, nir, prog_data, cfg, perf, stats,
diff --git a/src/intel/compiler/intel_clc.c b/src/intel/compiler/intel_clc.c
index 7633c90381d..0d554882a9b 100644
--- a/src/intel/compiler/intel_clc.c
+++ b/src/intel/compiler/intel_clc.c
@@ -183,7 +183,7 @@ print_cs_prog_data_fields(FILE *fp, const char *prefix, const char *pad,
 static void
 print_kernel(FILE *fp, const char *prefix,
              const struct brw_kernel *kernel,
-             const struct intel_device_info *devinfo)
+             const struct brw_isa_info *isa)
 {
    struct mesa_sha1 sha1_ctx;
    _mesa_sha1_init(&sha1_ctx);
@@ -231,7 +231,7 @@ print_kernel(FILE *fp, const char *prefix,
 
    fprintf(fp, "#if 0  /* BEGIN KERNEL ASSEMBLY */\n");
    fprintf(fp, "\n");
-   intel_disassemble(devinfo, kernel->code, 0, fp);
+   intel_disassemble(isa, kernel->code, 0, fp);
    fprintf(fp, "\n");
    fprintf(fp, "#endif /* END KERNEL ASSEMBLY */\n");
    print_u32_data(fp, prefix, "code", kernel->code,
@@ -386,6 +386,9 @@ int main(int argc, char **argv)
       return -1;
    }
 
+   struct brw_isa_info _isa, *isa = &_isa;
+   brw_init_isa_info(isa, devinfo);
+
    if (entry_point == NULL) {
       fprintf(stderr, "No entry-point name specified.\n");
       print_usage(argv[0], stderr);
@@ -559,10 +562,10 @@ int main(int argc, char **argv)
 
    if (outfile != NULL) {
       FILE *fp = fopen(outfile, "w");
-      print_kernel(fp, prefix, &kernel, devinfo);
+      print_kernel(fp, prefix, &kernel, isa);
       fclose(fp);
    } else {
-      print_kernel(stdout, prefix, &kernel, devinfo);
+      print_kernel(stdout, prefix, &kernel, isa);
    }
 
    ralloc_free(mem_ctx);
diff --git a/src/intel/compiler/test_eu_compact.cpp b/src/intel/compiler/test_eu_compact.cpp
index 16e2e4c6100..fde374739dc 100644
--- a/src/intel/compiler/test_eu_compact.cpp
+++ b/src/intel/compiler/test_eu_compact.cpp
@@ -59,12 +59,12 @@ test_compact_instruction(struct brw_codegen *p, brw_inst src)
    brw_compact_inst dst;
    memset(&dst, 0xd0, sizeof(dst));
 
-   if (brw_try_compact_instruction(p->devinfo, &dst, &src)) {
+   if (brw_try_compact_instruction(p->isa, &dst, &src)) {
       brw_inst uncompacted;
 
-      brw_uncompact_instruction(p->devinfo, &uncompacted, &dst);
+      brw_uncompact_instruction(p->isa, &uncompacted, &dst);
       if (memcmp(&uncompacted, &src, sizeof(src))) {
-	 brw_debug_compact_uncompact(p->devinfo, &src, &uncompacted);
+	 brw_debug_compact_uncompact(p->isa, &src, &uncompacted);
 	 return false;
       }
    } else {
@@ -74,7 +74,7 @@ test_compact_instruction(struct brw_codegen *p, brw_inst src)
       if (memcmp(&unchanged, &dst, sizeof(dst))) {
 	 fprintf(stderr, "Failed to compact, but dst changed\n");
 	 fprintf(stderr, "  Instruction: ");
-	 brw_disassemble_inst(stderr, p->devinfo, &src, false, 0, NULL);
+	 brw_disassemble_inst(stderr, p->isa, &src, false, 0, NULL);
 	 return false;
       }
    }
@@ -90,17 +90,19 @@ test_compact_instruction(struct brw_codegen *p, brw_inst src)
  * become meaningless once fuzzing twiddles a related bit.
  */
 static void
-clear_pad_bits(const struct intel_device_info *devinfo, brw_inst *inst)
+clear_pad_bits(const struct brw_isa_info *isa, brw_inst *inst)
 {
-   if (brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SEND &&
-       brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SENDC &&
+   const struct intel_device_info *devinfo = isa->devinfo;
+
+   if (brw_inst_opcode(isa, inst) != BRW_OPCODE_SEND &&
+       brw_inst_opcode(isa, inst) != BRW_OPCODE_SENDC &&
        brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE &&
        brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
       brw_inst_set_bits(inst, 127, 111, 0);
    }
 
    if (devinfo->ver == 8 && devinfo->platform != INTEL_PLATFORM_CHV &&
-       is_3src(devinfo, brw_inst_opcode(devinfo, inst))) {
+       is_3src(isa, brw_inst_opcode(isa, inst))) {
       brw_inst_set_bits(inst, 105, 105, 0);
       brw_inst_set_bits(inst, 84, 84, 0);
       brw_inst_set_bits(inst, 36, 35, 0);
@@ -108,8 +110,10 @@ clear_pad_bits(const struct intel_device_info *devinfo, brw_inst *inst)
 }
 
 static bool
-skip_bit(const struct intel_device_info *devinfo, brw_inst *src, int bit)
+skip_bit(const struct brw_isa_info *isa, brw_inst *src, int bit)
 {
+   const struct intel_device_info *devinfo = isa->devinfo;
+
    /* pad bit */
    if (bit == 7)
       return true;
@@ -118,7 +122,7 @@ skip_bit(const struct intel_device_info *devinfo, brw_inst *src, int bit)
    if (bit == 29)
       return true;
 
-   if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) {
+   if (is_3src(isa, brw_inst_opcode(isa, src))) {
       if (devinfo->ver >= 9 || devinfo->platform == INTEL_PLATFORM_CHV) {
          if (bit == 127)
             return true;
@@ -155,8 +159,8 @@ skip_bit(const struct intel_device_info *devinfo, brw_inst *src, int bit)
    }
 
    /* sometimes these are pad bits. */
-   if (brw_inst_opcode(devinfo, src) != BRW_OPCODE_SEND &&
-       brw_inst_opcode(devinfo, src) != BRW_OPCODE_SENDC &&
+   if (brw_inst_opcode(isa, src) != BRW_OPCODE_SEND &&
+       brw_inst_opcode(isa, src) != BRW_OPCODE_SENDC &&
        brw_inst_src0_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
        brw_inst_src1_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE &&
        bit >= 121) {
@@ -170,22 +174,22 @@ static bool
 test_fuzz_compact_instruction(struct brw_codegen *p, brw_inst src)
 {
    for (int bit0 = 0; bit0 < 128; bit0++) {
-      if (skip_bit(p->devinfo, &src, bit0))
+      if (skip_bit(p->isa, &src, bit0))
 	 continue;
 
       for (int bit1 = 0; bit1 < 128; bit1++) {
          brw_inst instr = src;
 	 uint64_t *bits = instr.data;
 
-         if (skip_bit(p->devinfo, &src, bit1))
+         if (skip_bit(p->isa, &src, bit1))
 	    continue;
 
 	 bits[bit0 / 64] ^= (1ull << (bit0 & 63));
 	 bits[bit1 / 64] ^= (1ull << (bit1 & 63));
 
-         clear_pad_bits(p->devinfo, &instr);
+         clear_pad_bits(p->isa, &instr);
 
-         if (!brw_validate_instruction(p->devinfo, &instr, 0, NULL))
+         if (!brw_validate_instruction(p->isa, &instr, 0, NULL))
             continue;
 
 	 if (!test_compact_instruction(p, instr)) {
@@ -209,7 +213,8 @@ protected:
       devinfo->verx10 = params.verx10;
       devinfo->ver = devinfo->verx10 / 10;
 
-      brw_init_codegen(devinfo, p, p);
+      brw_init_isa_info(&isa, devinfo);
+      brw_init_codegen(&isa, p, p);
       brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
       brw_set_default_access_mode(p, params.align);
    };
@@ -223,6 +228,7 @@ protected:
    };
 
    void *mem_ctx;
+   struct brw_isa_info isa;
    intel_device_info *devinfo;
    brw_codegen *p;
 };
diff --git a/src/intel/compiler/test_eu_validate.cpp b/src/intel/compiler/test_eu_validate.cpp
index ac1cad0d563..cef69aa936b 100644
--- a/src/intel/compiler/test_eu_validate.cpp
+++ b/src/intel/compiler/test_eu_validate.cpp
@@ -57,6 +57,7 @@ public:
    validation_test();
    virtual ~validation_test();
 
+   struct brw_isa_info isa;
    struct brw_codegen *p;
    struct intel_device_info devinfo;
 };
@@ -79,7 +80,9 @@ void validation_test::SetUp()
 
    intel_get_device_info_from_pci_id(devid, &devinfo);
 
-   brw_init_codegen(&devinfo, p, p);
+   brw_init_isa_info(&isa, &devinfo);
+
+   brw_init_codegen(&isa, p, p);
 }
 
 struct gfx_name {
@@ -98,14 +101,14 @@ static bool
 validate(struct brw_codegen *p)
 {
    const bool print = getenv("TEST_DEBUG");
-   struct disasm_info *disasm = disasm_initialize(p->devinfo, NULL);
+   struct disasm_info *disasm = disasm_initialize(p->isa, NULL);
 
    if (print) {
       disasm_new_inst_group(disasm, 0);
       disasm_new_inst_group(disasm, p->next_insn_offset);
    }
 
-   bool ret = brw_validate_instructions(p->devinfo, p->store, 0,
+   bool ret = brw_validate_instructions(p->isa, p->store, 0,
                                         p->next_insn_offset, disasm);
 
    if (print) {
@@ -180,7 +183,7 @@ TEST_P(validation_test, opcode46)
     *              reserved on Gen 7
     *              "goto" on Gfx8+
     */
-   brw_next_insn(p, brw_opcode_decode(&devinfo, 46));
+   brw_next_insn(p, brw_opcode_decode(&isa, 46));
 
    if (devinfo.ver == 7) {
       EXPECT_FALSE(validate(p));
@@ -2582,7 +2585,7 @@ TEST_P(validation_test, qword_low_power_no_64bit_arf)
          brw_MUL(p, retype(inst[i].dst, inst[i].dst_type),
                     retype(inst[i].src, inst[i].src_type),
                     retype(zero, inst[i].src_type));
-         brw_inst_set_opcode(&devinfo, last_inst, inst[i].opcode);
+         brw_inst_set_opcode(&isa, last_inst, inst[i].opcode);
       }
       brw_inst_set_exec_size(&devinfo, last_inst, inst[i].exec_size);
       brw_inst_set_acc_wr_control(&devinfo, last_inst, inst[i].acc_wr);
diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index c4bce95e9f4..cbe8a49f749 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -38,6 +38,7 @@
 #include <sys/wait.h>
 #include <sys/mman.h>
 
+#include "intel/compiler/brw_isa_info.h"
 #include "util/macros.h"
 
 #include "aub_read.h"
@@ -59,6 +60,7 @@ static enum { COLOR_AUTO, COLOR_ALWAYS, COLOR_NEVER } option_color;
 uint16_t pci_id = 0;
 char *input_file = NULL, *xml_path = NULL;
 struct intel_device_info devinfo;
+struct brw_isa_info isa;
 struct intel_batch_decode_ctx batch_ctx;
 struct aub_mem mem;
 
@@ -88,6 +90,8 @@ aubinator_init(void *user_data, int aub_pci_id, const char *app_name)
       exit(EXIT_FAILURE);
    }
 
+   brw_init_isa_info(&isa, &devinfo);
+
    enum intel_batch_decode_flags batch_flags = 0;
    if (option_color == COLOR_ALWAYS)
       batch_flags |= INTEL_BATCH_DECODE_IN_COLOR;
@@ -97,8 +101,8 @@ aubinator_init(void *user_data, int aub_pci_id, const char *app_name)
       batch_flags |= INTEL_BATCH_DECODE_OFFSETS;
    batch_flags |= INTEL_BATCH_DECODE_FLOATS;
 
-   intel_batch_decode_ctx_init(&batch_ctx, &devinfo, outfile, batch_flags,
-                               xml_path, NULL, NULL, NULL);
+   intel_batch_decode_ctx_init(&batch_ctx, &isa, &devinfo, outfile,
+                               batch_flags, xml_path, NULL, NULL, NULL);
 
    /* Check for valid spec instance, if wrong xml_path is passed then spec
     * instance is not initialized properly
diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c
index 155e99d7abd..74514f1de09 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -39,6 +39,7 @@
 #include <zlib.h>
 
 #include "common/intel_decoder.h"
+#include "compiler/brw_compiler.h"
 #include "dev/intel_debug.h"
 #include "util/macros.h"
 
@@ -418,6 +419,7 @@ read_data_file(FILE *file)
    bool ring_wraps = false;
    char *ring_name = NULL;
    struct intel_device_info devinfo;
+   struct brw_isa_info isa;
    uint64_t acthd = 0;
 
    while (getline(&line, &line_size, file) > 0) {
@@ -510,6 +512,8 @@ read_data_file(FILE *file)
 
             printf("Detected GEN%i chipset\n", devinfo.ver);
 
+            brw_init_isa_info(&isa, &devinfo);
+
             if (xml_path == NULL)
                spec = intel_spec_load(&devinfo);
             else
@@ -674,8 +678,9 @@ read_data_file(FILE *file)
    batch_flags |= INTEL_BATCH_DECODE_FLOATS;
 
    struct intel_batch_decode_ctx batch_ctx;
-   intel_batch_decode_ctx_init(&batch_ctx, &devinfo, stdout, batch_flags,
-                               xml_path, get_intel_batch_bo, NULL, NULL);
+   intel_batch_decode_ctx_init(&batch_ctx, &isa, &devinfo, stdout,
+                               batch_flags, xml_path, get_intel_batch_bo,
+                               NULL, NULL);
    batch_ctx.acthd = acthd;
 
 
diff --git a/src/intel/tools/aubinator_viewer.cpp b/src/intel/tools/aubinator_viewer.cpp
index 493eb9cf764..ec03238f981 100644
--- a/src/intel/tools/aubinator_viewer.cpp
+++ b/src/intel/tools/aubinator_viewer.cpp
@@ -62,6 +62,7 @@ struct aub_file {
 
    /* Device state */
    struct intel_device_info devinfo;
+   struct brw_isa_info isa;
    struct intel_spec *spec;
 };
 
@@ -129,6 +130,7 @@ handle_info(void *user_data, int pci_id, const char *app_name)
       fprintf(stderr, "can't find device information: pci_id=0x%x\n", file->pci_id);
       exit(EXIT_FAILURE);
    }
+   brw_init_isa_info(&file->isa, &file->devinfo);
    file->spec = intel_spec_load(&file->devinfo);
 }
 
@@ -392,7 +394,7 @@ new_shader_window(struct aub_mem *mem, uint64_t address, const char *desc)
    if (shader_bo.map) {
       FILE *f = open_memstream(&window->shader, &window->shader_size);
       if (f) {
-         intel_disassemble(&context.file->devinfo,
+         intel_disassemble(&context.file->isa,
                            (const uint8_t *) shader_bo.map +
                            (address - shader_bo.addr), 0, f);
          fclose(f);
diff --git a/src/intel/tools/i965_asm.c b/src/intel/tools/i965_asm.c
index 95987ac364b..713a99a6c5a 100644
--- a/src/intel/tools/i965_asm.c
+++ b/src/intel/tools/i965_asm.c
@@ -142,7 +142,7 @@ i965_postprocess_labels()
             int relative_offset = (tlabel->offset - ilabel->offset) / sizeof(brw_inst);
             relative_offset *= to_bytes_scale;
 
-            unsigned opcode = brw_inst_opcode(p->devinfo, inst);
+            unsigned opcode = brw_inst_opcode(p->isa, inst);
 
             if (ilabel->type == INSTR_LABEL_JIP) {
                switch (opcode) {
@@ -309,8 +309,11 @@ int main(int argc, char **argv)
       goto end;
    }
 
+   struct brw_isa_info isa;
+   brw_init_isa_info(&isa, devinfo);
+
    p = rzalloc(NULL, struct brw_codegen);
-   brw_init_codegen(devinfo, p, p);
+   brw_init_codegen(&isa, p, p);
    p->automatic_exec_sizes = false;
 
    err = yyparse();
@@ -322,7 +325,7 @@ int main(int argc, char **argv)
 
    store = p->store;
 
-   disasm_info = disasm_initialize(p->devinfo, NULL);
+   disasm_info = disasm_initialize(p->isa, NULL);
    if (!disasm_info) {
       fprintf(stderr, "Unable to initialize disasm_info struct instance\n");
       goto end;
@@ -331,7 +334,7 @@ int main(int argc, char **argv)
    if (output_type == OPT_OUTPUT_C_LITERAL)
       fprintf(output, "{\n");
 
-   brw_validate_instructions(p->devinfo, p->store, 0,
+   brw_validate_instructions(p->isa, p->store, 0,
                              p->next_insn_offset, disasm_info);
 
    const int nr_insn = (p->next_insn_offset - start_offset) / 16;
diff --git a/src/intel/tools/i965_disasm.c b/src/intel/tools/i965_disasm.c
index 7a9f496b4fa..e09d8d286a5 100644
--- a/src/intel/tools/i965_disasm.c
+++ b/src/intel/tools/i965_disasm.c
@@ -208,6 +208,9 @@ int main(int argc, char *argv[])
       exit(EXIT_FAILURE);
    }
 
+   struct brw_isa_info isa;
+   brw_init_isa_info(&isa, &devinfo);
+
    if (input_type == OPT_INPUT_BINARY)
       assembly = i965_disasm_read_binary(fp, &end);
    else if (input_type == OPT_INPUT_C_LITERAL)
@@ -223,7 +226,7 @@ int main(int argc, char *argv[])
    }
 
    /* Disassemble i965 instructions from buffer assembly */
-   brw_disassemble_with_labels(&devinfo, assembly, start, end, stdout);
+   brw_disassemble_with_labels(&isa, assembly, start, end, stdout);
 
    result = EXIT_SUCCESS;
 
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index caa1e22d98b..5f361d35906 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -3086,6 +3086,7 @@ VkResult anv_CreateDevice(
          INTEL_BATCH_DECODE_FLOATS;
 
       intel_batch_decode_ctx_init(&device->decoder_ctx,
+                                  &physical_device->compiler->isa,
                                   &physical_device->info,
                                   stderr, decode_flags, NULL,
                                   decode_get_bo, NULL, device);
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 5ed079eba5c..89af33110f2 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -1275,7 +1275,7 @@ anv_pipeline_add_executable(struct anv_pipeline *pipeline,
       /* Creating this is far cheaper than it looks.  It's perfectly fine to
        * do it for every binary.
        */
-      intel_disassemble(&pipeline->device->info,
+      intel_disassemble(&pipeline->device->physical->compiler->isa,
                         stage->code, code_offset, stream);
 
       fclose(stream);
diff --git a/src/intel/vulkan/anv_pipeline_cache.c b/src/intel/vulkan/anv_pipeline_cache.c
index 639879f642e..e85a362f7f4 100644
--- a/src/intel/vulkan/anv_pipeline_cache.c
+++ b/src/intel/vulkan/anv_pipeline_cache.c
@@ -142,7 +142,8 @@ anv_shader_bin_create(struct anv_device *device,
       };
    }
 
-   brw_write_shader_relocs(&device->info, shader->kernel.map, prog_data_in,
+   brw_write_shader_relocs(&device->physical->compiler->isa,
+                           shader->kernel.map, prog_data_in,
                            reloc_values, rv_count);
 
    memcpy(prog_data, prog_data_in, prog_data_size);