diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c
index 3c84548d881..aabcd7056e5 100644
--- a/src/intel/dev/intel_device_info.c
+++ b/src/intel/dev/intel_device_info.c
@@ -985,10 +985,10 @@ static const struct intel_device_info intel_device_info_ehl_2x4 = {
    .simulator_id = 22,                                          \
    .max_eus_per_subslice = 16,                                  \
    .pat = {                                                     \
-         .cached_coherent = PAT_ENTRY(0, WB, 2WAY),             \
-         .scanout = PAT_ENTRY(1, WC, NONE),                     \
-         .writeback_incoherent = PAT_ENTRY(0, WB, 2WAY),        \
-         .writecombining = PAT_ENTRY(1, WC, NONE),              \
+         .cached_coherent = PAT_ENTRY(0, WB),                   \
+         .scanout = PAT_ENTRY(1, WC),                           \
+         .writeback_incoherent = PAT_ENTRY(0, WB),              \
+         .writecombining = PAT_ENTRY(1, WC),                    \
    },                                                           \
    .cooperative_matrix_configurations = {                       \
     { INTEL_CMAT_SCOPE_SUBGROUP, 8, 8, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT32, INTEL_CMAT_FLOAT32 }, \
@@ -1130,10 +1130,10 @@ static const struct intel_device_info intel_device_info_sg1 = {
    .has_flat_ccs = true,                                        \
    /* There is no PAT table for DG2, using TGL ones */          \
    .pat = {                                                     \
-         .cached_coherent = PAT_ENTRY(0, WB, 1WAY),             \
-         .scanout = PAT_ENTRY(1, WC, NONE),                     \
-         .writeback_incoherent = PAT_ENTRY(0, WB, 2WAY),        \
-         .writecombining = PAT_ENTRY(1, WC, NONE),              \
+         .cached_coherent = PAT_ENTRY(0, WB),                   \
+         .scanout = PAT_ENTRY(1, WC),                           \
+         .writeback_incoherent = PAT_ENTRY(0, WB),              \
+         .writecombining = PAT_ENTRY(1, WC),                    \
    }
 
 static const struct intel_device_info intel_device_info_dg2_g10 = {
@@ -1173,10 +1173,10 @@ static const struct intel_device_info intel_device_info_atsm_g11 = {
    .has_mesh_shading = true,                                    \
    .has_ray_tracing = true,                                     \
    .pat = {                                                     \
-         .cached_coherent = PAT_ENTRY(3, WB, 1WAY),             \
-         .scanout = PAT_ENTRY(1, WC, NONE),                     \
-         .writeback_incoherent = PAT_ENTRY(0, WB, NONE),        \
-         .writecombining = PAT_ENTRY(1, WC, NONE),              \
+         .cached_coherent = PAT_ENTRY(3, WB),                   \
+         .scanout = PAT_ENTRY(1, WC),                           \
+         .writeback_incoherent = PAT_ENTRY(0, WB),              \
+         .writecombining = PAT_ENTRY(1, WC),                    \
    }
 
 static const struct intel_device_info intel_device_info_mtl_u = {
@@ -1214,11 +1214,11 @@ static const struct intel_device_info intel_device_info_arl_h = {
    .has_ray_tracing = true,                                     \
    .has_indirect_unroll = true,                                 \
    .pat = {                                                     \
-      .cached_coherent = PAT_ENTRY(1, WB, 1WAY),                \
-      .scanout = PAT_ENTRY(6, WC, NONE),                        \
-      .writeback_incoherent = PAT_ENTRY(0, WB, NONE),           \
-      .writecombining = PAT_ENTRY(6, WC, NONE),                 \
-      .compressed = PAT_ENTRY(11, WC, NONE)                     \
+      .cached_coherent = PAT_ENTRY(1, WB),                      \
+      .scanout = PAT_ENTRY(6, WC),                              \
+      .writeback_incoherent = PAT_ENTRY(0, WB),                 \
+      .writecombining = PAT_ENTRY(6, WC),                       \
+      .compressed = PAT_ENTRY(11, WC)                           \
    },                                                           \
    .cooperative_matrix_configurations = {                       \
     { INTEL_CMAT_SCOPE_SUBGROUP, 8, 16, 16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT16, INTEL_CMAT_FLOAT32, INTEL_CMAT_FLOAT32 }, \
diff --git a/src/intel/dev/intel_device_info.h b/src/intel/dev/intel_device_info.h
index 9f99ca95d53..784646a9e96 100644
--- a/src/intel/dev/intel_device_info.h
+++ b/src/intel/dev/intel_device_info.h
@@ -64,11 +64,10 @@ extern "C" {
 #define intel_device_info_is_mtl_or_arl(devinfo) \
    (intel_device_info_is_mtl(devinfo) || intel_device_info_is_arl(devinfo))
 
-#define PAT_ENTRY(index_, mmap_, coh_)                      \
+#define PAT_ENTRY(index_, mmap_)                            \
 {                                                           \
    .index = index_,                                         \
-   .mmap = INTEL_DEVICE_INFO_MMAP_MODE_##mmap_,             \
-   .coherency = INTEL_DEVICE_INFO_COHERENCY_MODE_##coh_     \
+   .mmap = INTEL_DEVICE_INFO_MMAP_MODE_##mmap_              \
 }
 
 #ifdef GFX_VER
diff --git a/src/intel/dev/intel_device_info.py b/src/intel/dev/intel_device_info.py
index e09bf454f2a..8faa721f1a8 100644
--- a/src/intel/dev/intel_device_info.py
+++ b/src/intel/dev/intel_device_info.py
@@ -147,20 +147,12 @@ Enum("intel_device_info_mmap_mode",
        "INTEL_DEVICE_INFO_MMAP_MODE_WB"
        ])
 
-Enum("intel_device_info_coherency_mode",
-     [EnumValue("INTEL_DEVICE_INFO_COHERENCY_MODE_NONE", value=0),
-      EnumValue("INTEL_DEVICE_INFO_COHERENCY_MODE_1WAY", comment="CPU caches are snooped by GPU"),
-      EnumValue("INTEL_DEVICE_INFO_COHERENCY_MODE_2WAY",
-                comment="Fully coherent between GPU and CPU")
-      ])
-
 Struct("intel_device_info_pat_entry",
        [Member("uint8_t", "index"),
         Member("intel_device_info_mmap_mode", "mmap",
                comment=dedent("""\
                This tells KMD what caching mode the CPU mapping should use.
-               It has nothing to do with any PAT cache modes.""")),
-        Member("intel_device_info_coherency_mode", "coherency")])
+               It has nothing to do with any PAT cache modes."""))])
 
 Enum("intel_cmat_scope",
      [EnumValue("INTEL_CMAT_SCOPE_NONE", value=0),