From 72362f2830b78840fd413e23137a1f52e40d5b97 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
Date: Fri, 7 May 2021 03:57:36 -0400
Subject: [PATCH] amd/registers: don't generate 32-bit register fields
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This removes confusing register types due to deduplication, such as:
   "name": "SQ_WAVE_TTMP10",
   "type_ref": "SPI_SHADER_USER_DATA_PS_0"

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
---
 src/amd/registers/parse_kernel_headers.py | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/amd/registers/parse_kernel_headers.py b/src/amd/registers/parse_kernel_headers.py
index ed86cebc995..cdfbcb9f843 100644
--- a/src/amd/registers/parse_kernel_headers.py
+++ b/src/amd/registers/parse_kernel_headers.py
@@ -804,7 +804,12 @@ def generate_json(gfx_version, amd_headers_path):
 
         if len(type['fields']) > 0:
             reg_types[name] = type
-            reg['type_ref'] = name
+
+            # Don't define types that have only one field covering all bits
+            field0_bits = type['fields'][0]['bits'];
+            if len(type['fields']) > 1 or field0_bits[0] != 0 or field0_bits[1] != 31:
+                reg['type_ref'] = name
+
             reg_mappings.append(reg)