diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index e1745976f7e..60aa91ab0ed 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -3884,7 +3884,7 @@ isl_surf_get_ccs_surf(const struct isl_device *dev, isl_gfx30_##func(__VA_ARGS__); \ break; \ default: \ - assert(!"Unknown hardware generation"); \ + unreachable("Unknown hardware generation"); \ } /** diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c index 1bb595be22d..e842ac63aa5 100644 --- a/src/intel/isl/isl_format.c +++ b/src/intel/isl/isl_format.c @@ -1087,8 +1087,7 @@ isl_format_has_color_component(enum isl_format fmt, int component) case 3: return (fmtl->channels.a.bits + intensity) > 0; default: - assert(!"Invalid color component: must be 0..3"); - return false; + unreachable("Invalid color component: must be 0..3"); } } @@ -1212,8 +1211,7 @@ isl_format_rgbx_to_rgba(enum isl_format rgbx) case ISL_FORMAT_B5G5R5X1_UNORM_SRGB: return ISL_FORMAT_B5G5R5A1_UNORM_SRGB; default: - assert(!"Invalid RGBX format"); - return rgbx; + unreachable("Invalid RGBX format"); } } diff --git a/src/intel/isl/isl_priv.h b/src/intel/isl/isl_priv.h index 16e977bbf55..332900b17f8 100644 --- a/src/intel/isl/isl_priv.h +++ b/src/intel/isl/isl_priv.h @@ -82,8 +82,7 @@ typedef void (*isl_emit_cpb_control_s_func)(const struct isl_device *dev, void * case 300: \ return isl_gfx30_##func; \ default: \ - assert(!"Unknown hardware generation"); \ - return NULL; \ + unreachable("Unknown hardware generation"); \ } \ } diff --git a/src/intel/isl/isl_storage_image.c b/src/intel/isl/isl_storage_image.c index 50b39d959b3..492e901cf7b 100644 --- a/src/intel/isl/isl_storage_image.c +++ b/src/intel/isl/isl_storage_image.c @@ -228,8 +228,7 @@ isl_lower_storage_image_format(const struct intel_device_info *devinfo, return ISL_FORMAT_R32G32_UINT; default: - assert(!"Unknown image format"); - return ISL_FORMAT_UNSUPPORTED; + unreachable("Unknown image format"); } } @@ -338,7 +337,7 @@ isl_surf_fill_image_param(const struct isl_device *dev, break; default: - assert(!"Unhandled storage image tiling"); + unreachable("Unhandled storage image tiling"); } /* 3D textures are arranged in 2D in memory with 2^lod slices per row. The diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c index 68fbaa8479b..de9318758f7 100644 --- a/src/intel/isl/isl_surface_state.c +++ b/src/intel/isl/isl_surface_state.c @@ -747,8 +747,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state, case ISL_FORMAT_R16_UNORM: break; default: - assert(!"Incompatible HiZ Sampling format"); - break; + unreachable("Incompatible HiZ Sampling format"); } }