diff --git a/src/freedreno/afuc/emu-regs.c b/src/freedreno/afuc/emu-regs.c
index 6e039a68610..b87a1c84156 100644
--- a/src/freedreno/afuc/emu-regs.c
+++ b/src/freedreno/afuc/emu-regs.c
@@ -160,11 +160,22 @@ emu_get_gpu_reg(struct emu *emu, unsigned n)
 void
 emu_set_gpu_reg(struct emu *emu, unsigned n, uint32_t val)
 {
+   EMU_GPU_REG(CP_LPAC_SQE_CNTL);
+   EMU_CONTROL_REG(THREAD_SYNC);
+
    if (n >= ARRAY_SIZE(emu->gpu_regs.val))
       return;
    assert(n < ARRAY_SIZE(emu->gpu_regs.val));
    BITSET_SET(emu->gpu_regs.written, n);
    emu->gpu_regs.val[n] = val;
+
+   if (n == emu_reg_offset(&CP_LPAC_SQE_CNTL)) {
+      /* This is sort-of a hack, but emulate what the LPAC bootstrap routine
+       * does so that the main bootstrap routine doesn't get stuck.
+       */
+      emu_set_reg32(emu, &THREAD_SYNC,
+                    emu_get_reg32(emu, &THREAD_SYNC) | (1u << 1));
+   }
 }
 
 static bool
diff --git a/src/freedreno/afuc/emu.c b/src/freedreno/afuc/emu.c
index b5bc332f8cf..58a2cbcc25b 100644
--- a/src/freedreno/afuc/emu.c
+++ b/src/freedreno/afuc/emu.c
@@ -461,10 +461,16 @@ void
 emu_run_bootstrap(struct emu *emu)
 {
    EMU_CONTROL_REG(PACKET_TABLE_WRITE_ADDR);
+   EMU_CONTROL_REG(THREAD_SYNC);
 
    emu->quiet = true;
    emu->run_mode = true;
 
+   if (gpuver == 6 && emu->processor == EMU_PROC_LPAC) {
+      /* Emulate what the SQE bootstrap routine does after launching LPAC */
+      emu_set_reg32(emu, &THREAD_SYNC, 1u << 0);
+   }
+
    while (emu_get_reg32(emu, &PACKET_TABLE_WRITE_ADDR) < 0x80) {
       emu_step(emu);
    }
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 655239e4fec..3d6968a83bf 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1458,6 +1458,7 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/>
 	<reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/>
 	<reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/>
+	<reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/>
 	<reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/>
 	<reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 	<reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/>
diff --git a/src/freedreno/registers/adreno/adreno_control_regs.xml b/src/freedreno/registers/adreno/adreno_control_regs.xml
index aa4f695a9c6..59450d4d2e3 100644
--- a/src/freedreno/registers/adreno/adreno_control_regs.xml
+++ b/src/freedreno/registers/adreno/adreno_control_regs.xml
@@ -271,6 +271,8 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
 
 	<!-- new in gen3+ -->
 	<reg32 name="PRED_REG" offset="0x17f"/>
+
+	<reg32 name="THREAD_SYNC" offset="0x200"/>
 </domain>
 
 <domain name="A7XX_CONTROL_REG" width="32">