AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

aco: use instruction cast methods

Browse Source 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8595>
This commit is contained in:
Rhys Perry
2021-01-20 14:49:08 +00:00
committed by Marge Bot
parent fb12302b8e
commit 70dbcfa1c9
20 changed files with 190 additions and 211 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/compiler/aco_instruction_selection.cpp
+14 -17
View File
@@ -1224,7 +1224,7 @@ Temp emit_floor_f64(isel_context *ctx, Builder& bld, Definition dst, Temp val)
Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), dst0, dst1);
Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src0, v);
static_cast<VOP3_instruction*>(add)->neg[1] = true;
add->vop3()->neg[1] = true;
return add->definitions[0].getTemp();
}
@@ -1692,7 +1692,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
std::swap(src0, src1);
add_instr = bld.vop2_e64(aco_opcode::v_add_u16, Definition(dst), src0, as_vgpr(ctx, src1)).instr;
}
static_cast<VOP3_instruction*>(add_instr)->clamp = 1;
add_instr->vop3()->clamp = 1;
} else if (dst.regClass() == v1) {
if (ctx->options->chip_class >= GFX9) {
aco_ptr<VOP3_instruction> add{create_instruction<VOP3_instruction>(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)};
@@ -1944,7 +1944,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
case nir_op_fsub: {
if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) {
Instruction* add = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_f16, dst);
VOP3P_instruction* sub = static_cast<VOP3P_instruction*>(add);
VOP3P_instruction* sub = add->vop3p();
sub->neg_lo[1] = true;
sub->neg_hi[1] = true;
break;
@@ -1965,8 +1965,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
} else if (dst.regClass() == v2) {
Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst),
as_vgpr(ctx, src0), as_vgpr(ctx, src1));
VOP3_instruction* sub = static_cast<VOP3_instruction*>(add);
sub->neg[1] = true;
add->vop3()->neg[1] = true;
} else {
isel_err(&instr->instr, "Unimplemented NIR instr bit size");
}
@@ -2102,7 +2101,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
Temp src = get_alu_src_vop3p(ctx, instr->src[0]);
Instruction* vop3p = bld.vop3p(aco_opcode::v_pk_mul_f16, Definition(dst), src, Operand(uint16_t(0x3C00)),
instr->src[0].swizzle[0] & 1, instr->src[0].swizzle[1] & 1);
static_cast<VOP3P_instruction*>(vop3p)->clamp = true;
vop3p->vop3p()->clamp = true;
emit_split_vector(ctx, dst, 2);
break;
}
@@ -2115,8 +2114,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
// TODO: confirm that this holds under any circumstances
} else if (dst.regClass() == v2) {
Instruction* add = bld.vop3(aco_opcode::v_add_f64, Definition(dst), src, Operand(0u));
VOP3_instruction* vop3 = static_cast<VOP3_instruction*>(add);
vop3->clamp = true;
add->vop3()->clamp = true;
} else {
isel_err(&instr->instr, "Unimplemented NIR instr bit size");
}
@@ -2255,12 +2253,12 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
Temp bfi = bld.vop3(aco_opcode::v_bfi_b32, bld.def(v1), bitmask, bld.copy(bld.def(v1), Operand(0x43300000u)), as_vgpr(ctx, src0_hi));
Temp tmp = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), src0, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
Instruction *sub = bld.vop3(aco_opcode::v_add_f64, bld.def(v2), tmp, bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(0u), bfi));
static_cast<VOP3_instruction*>(sub)->neg[1] = true;
sub->vop3()->neg[1] = true;
tmp = sub->definitions[0].getTemp();
Temp v = bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), Operand(-1u), Operand(0x432fffffu));
Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_gt_f64, bld.hint_vcc(bld.def(bld.lm)), src0, v);
static_cast<VOP3_instruction*>(vop3)->abs[0] = true;
vop3->vop3()->abs[0] = true;
Temp cond = vop3->definitions[0].getTemp();
Temp tmp_lo = bld.tmp(v1), tmp_hi = bld.tmp(v1);
@@ -2926,7 +2924,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr)
f32 = bld.vop1(aco_opcode::v_cvt_f32_f16, bld.def(v1), f16);
Temp smallest = bld.copy(bld.def(s1), Operand(0x38800000u));
Instruction* vop3 = bld.vopc_e64(aco_opcode::v_cmp_nlt_f32, bld.hint_vcc(bld.def(bld.lm)), f32, smallest);
static_cast<VOP3_instruction*>(vop3)->abs[0] = true;
vop3->vop3()->abs[0] = true;
cmp_res = vop3->definitions[0].getTemp();
}
@@ -3517,7 +3515,7 @@ Temp lds_load_callback(Builder& bld, const LoadEmitInfo &info,
instr = bld.ds(op, Definition(val), offset, m, const_offset, const_offset + 1);
else
instr = bld.ds(op, Definition(val), offset, m, const_offset);
static_cast<DS_instruction *>(instr)->sync = info.sync;
instr->ds()->sync = info.sync;
if (size < 4)
val = bld.pseudo(aco_opcode::p_extract_vector, bld.def(RegClass::get(RegType::vgpr, size)), val, Operand(0u));
@@ -3933,8 +3931,7 @@ void store_lds(isel_context *ctx, unsigned elem_size_bytes, Temp data, uint32_t
} else {
instr = bld.ds(op, address_offset, split_data, m, inline_offset);
}
static_cast<DS_instruction *>(instr)->sync =
memory_sync_info(storage_shared);
instr->ds()->sync = memory_sync_info(storage_shared);
}
}
@@ -4097,7 +4094,7 @@ void emit_single_mubuf_store(isel_context *ctx, Temp descriptor, Temp voffset, T
/* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
/* dlc*/ false, /* slc */ slc);
static_cast<MUBUF_instruction *>(r.instr)->sync = sync;
r.instr->mubuf()->sync = sync;
}
void store_vmem_mubuf(isel_context *ctx, Temp src, Temp descriptor, Temp voffset, Temp soffset,
@@ -5506,7 +5503,7 @@ void visit_load_push_constant(isel_context *ctx, nir_intrinsic_instr *instr)
unreachable("unimplemented or forbidden load_push_constant.");
}
static_cast<SMEM_instruction*>(bld.smem(op, Definition(vec), ptr, index).instr)->prevent_overflow = true;
bld.smem(op, Definition(vec), ptr, index).instr->smem()->prevent_overflow = true;
if (!aligned) {
Operand byte_offset = index_cv ? Operand((offset + index_cv->u32) % 4) : Operand(index);
@@ -7150,7 +7147,7 @@ void visit_store_scratch(isel_context *ctx, nir_intrinsic_instr *instr) {
for (unsigned i = 0; i < write_count; i++) {
aco_opcode op = get_buffer_store_op(write_datas[i].bytes());
Instruction *mubuf = bld.mubuf(op, rsrc, offset, ctx->program->scratch_offset, write_datas[i], offsets[i], true, true);
static_cast<MUBUF_instruction *>(mubuf)->sync = memory_sync_info(storage_scratch, semantic_private);
mubuf->mubuf()->sync = memory_sync_info(storage_scratch, semantic_private);
}
}