diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index a6d77035fab..d22d61a2da0 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -312,12 +312,6 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
    state[0] = va >> 8;
    state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
 
-   /* Only macrotiled modes can set tile swizzle.
-    * GFX9 doesn't use (legacy) base_level_info.
-    */
-   if (sscreen->info.gfx_level >= GFX9 || base_level_info->mode == RADEON_SURF_MODE_2D)
-      state[0] |= tex->surface.tile_swizzle;
-
    if (sscreen->info.gfx_level >= GFX8) {
       if (!(access & SI_IMAGE_ACCESS_DCC_OFF) && vi_dcc_enabled(tex, first_level)) {
          meta_va = tex->buffer.gpu_address + tex->surface.meta_offset;
@@ -334,15 +328,11 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
                                             is_stencil ? PIPE_MASK_S : PIPE_MASK_Z)) {
          meta_va = tex->buffer.gpu_address + tex->surface.meta_offset;
       }
-
-      if (meta_va)
-         state[6] |= S_008F28_COMPRESSION_EN(1);
    }
 
-   if (sscreen->info.gfx_level >= GFX8 && sscreen->info.gfx_level <= GFX9)
-      state[7] = meta_va >> 8;
-
    if (sscreen->info.gfx_level >= GFX10) {
+      state[0] |= tex->surface.tile_swizzle;
+
       if (is_stencil) {
          state[3] |= S_00A00C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode);
       } else {
@@ -358,7 +348,8 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
          if (!tex->is_depth && tex->surface.meta_offset)
             meta = tex->surface.u.gfx9.color.dcc;
 
-         state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
+         state[6] |= S_00A018_COMPRESSION_EN(1) |
+                     S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
                      S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8) |
                      /* DCC image stores require the following settings:
                       * - INDEPENDENT_64B_BLOCKS = 0
@@ -375,10 +366,12 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
          /* TC-compatible MSAA HTILE requires ITERATE_256. */
          if (tex->is_depth && tex->buffer.b.b.nr_samples >= 2)
             state[6] |= S_00A018_ITERATE_256(1);
-      }
 
-      state[7] = meta_va >> 16;
+         state[7] = meta_va >> 16;
+      }
    } else if (sscreen->info.gfx_level == GFX9) {
+      state[0] |= tex->surface.tile_swizzle;
+
       if (is_stencil) {
          state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode);
          state[4] |= S_008F20_PITCH(tex->surface.u.gfx9.zs.stencil_epitch);
@@ -397,8 +390,6 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
          state[4] |= S_008F20_PITCH(epitch);
       }
 
-      state[5] &=
-         C_008F24_META_DATA_ADDRESS & C_008F24_META_PIPE_ALIGNED & C_008F24_META_RB_ALIGNED;
       if (meta_va) {
          struct gfx9_surf_meta_flags meta = {
             .rb_aligned = 1,
@@ -411,14 +402,25 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
          state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
                      S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
                      S_008F24_META_RB_ALIGNED(meta.rb_aligned);
+         state[6] |= S_008F28_COMPRESSION_EN(1);
+         state[7] = meta_va >> 8;
       }
    } else {
       /* GFX6-GFX8 */
       unsigned pitch = base_level_info->nblk_x * block_width;
       unsigned index = si_tile_mode_index(tex, base_level, is_stencil);
 
+      /* Only macrotiled modes can set tile swizzle. */
+      if (base_level_info->mode == RADEON_SURF_MODE_2D)
+         state[0] |= tex->surface.tile_swizzle;
+
       state[3] |= S_008F1C_TILING_INDEX(index);
       state[4] |= S_008F20_PITCH(pitch - 1);
+
+      if (sscreen->info.gfx_level == GFX8 && meta_va) {
+         state[6] |= S_008F28_COMPRESSION_EN(1);
+         state[7] = meta_va >> 8;
+      }
    }
 
    if (tex->swap_rgb_to_bgr) {