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intel/compiler: Add support for ternary add instruction on XeHP

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v2:
- Re-arragne opcode in correct order (Matt Turner)
- Move ADD3 case closer to LRP (Jason)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11596>
This commit is contained in:
Sagar Ghuge
2020-06-05 22:40:26 -07:00
committed by Marge Bot
parent e8dff256c0
commit 705285b9f4
9 changed files with 18 additions and 0 deletions
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src/intel/compiler/brw_shader.cpp
+3
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@@ -866,6 +866,7 @@ backend_instruction::is_commutative() const
case BRW_OPCODE_OR:
case BRW_OPCODE_XOR:
case BRW_OPCODE_ADD:
case BRW_OPCODE_ADD3:
case BRW_OPCODE_MUL:
case SHADER_OPCODE_MULH:
return true;
@@ -983,6 +984,7 @@ backend_instruction::can_do_saturate() const
{
switch (opcode) {
case BRW_OPCODE_ADD:
case BRW_OPCODE_ADD3:
case BRW_OPCODE_ASR:
case BRW_OPCODE_AVG:
case BRW_OPCODE_CSEL:
@@ -1028,6 +1030,7 @@ backend_instruction::can_do_cmod() const
{
switch (opcode) {
case BRW_OPCODE_ADD:
case BRW_OPCODE_ADD3:
case BRW_OPCODE_ADDC:
case BRW_OPCODE_AND:
case BRW_OPCODE_ASR: