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intel/compiler: Add support for ternary add instruction on XeHP

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v2:
- Re-arragne opcode in correct order (Matt Turner)
- Move ADD3 case closer to LRP (Jason)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11596>
This commit is contained in:
Sagar Ghuge
2020-06-05 22:40:26 -07:00
committed by Marge Bot
parent e8dff256c0
commit 705285b9f4
9 changed files with 18 additions and 0 deletions
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src/intel/compiler/brw_ir_performance.cpp
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@@ -378,6 +378,7 @@ namespace {
case BRW_OPCODE_MOV:
case BRW_OPCODE_CMP:
case BRW_OPCODE_ADD:
case BRW_OPCODE_ADD3:
case BRW_OPCODE_MUL:
case SHADER_OPCODE_MOV_RELOC_IMM:
case VEC4_OPCODE_MOV_FOR_SCRATCH: