intel/compiler: Add support for ternary add instruction on XeHP

v2:
- Re-arragne opcode in correct order (Matt Turner)
- Move ADD3 case closer to LRP (Jason)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11596>

src/intel/compiler/brw_fs_generator.cpp

@@ -2090,6 +2090,11 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
          brw_LRP(p, dst, src[0], src[1], src[2]);
 	 break;
 
+      case BRW_OPCODE_ADD3:
+         assert(devinfo->verx10 >= 125);
+         brw_ADD3(p, dst, src[0], src[1], src[2]);
+         break;
+
       case BRW_OPCODE_FRC:
 	 brw_FRC(p, dst, src[0]);
 	 break;