i965: Move the back-end compiler to src/intel/compiler
Mostly a dummy git mv with a couple of noticable parts: - With the earlier header cleanups, nothing in src/intel depends files from src/mesa/drivers/dri/i965/ - Both Autoconf and Android builds are addressed. Thanks to Mauro and Tapani for the fixups in the latter - brw_util.[ch] is not really compiler specific, so it's moved to i965. v2: - move brw_eu_defines.h instead of brw_defines.h - remove no-longer applicable includes - add missing vulkan/ prefix in the Android build (thanks Tapani) v3: - don't list brw_defines.h in src/intel/Makefile.sources (Jason) - rebase on top of the oa patches [Emil Velikov: commit message, various small fixes througout] Signed-off-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
This commit is contained in:
Jason Ekstrand
committed by
Emil Velikov
Emil Velikov
parent
d0d4a5f43b
commit
700bebb958
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "brw_vec4.h"
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#include "brw_vec4_live_variables.h"
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#include "brw_cfg.h"
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/** @file brw_vec4_dead_code_eliminate.cpp
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*
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* Dataflow-aware dead code elimination.
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*
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* Walks the instruction list from the bottom, removing instructions that
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* have results that both aren't used in later blocks and haven't been read
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* yet in the tail end of this block.
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*/
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using namespace brw;
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bool
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vec4_visitor::dead_code_eliminate()
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{
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bool progress = false;
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calculate_live_intervals();
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int num_vars = live_intervals->num_vars;
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BITSET_WORD *live = rzalloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars));
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BITSET_WORD *flag_live = rzalloc_array(NULL, BITSET_WORD, 1);
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foreach_block_reverse_safe(block, cfg) {
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memcpy(live, live_intervals->block_data[block->num].liveout,
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sizeof(BITSET_WORD) * BITSET_WORDS(num_vars));
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memcpy(flag_live, live_intervals->block_data[block->num].flag_liveout,
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sizeof(BITSET_WORD));
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foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) {
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if ((inst->dst.file == VGRF && !inst->has_side_effects()) ||
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(inst->dst.is_null() && inst->writes_flag())){
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bool result_live[4] = { false };
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if (inst->dst.file == VGRF) {
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for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) {
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for (int c = 0; c < 4; c++) {
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const unsigned v = var_from_reg(alloc, inst->dst, c, i);
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result_live[c] |= BITSET_TEST(live, v);
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}
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}
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} else {
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for (unsigned c = 0; c < 4; c++)
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result_live[c] = BITSET_TEST(flag_live, c);
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}
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/* If the instruction can't do writemasking, then it's all or
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* nothing.
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*/
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if (!inst->can_do_writemask(devinfo)) {
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bool result = result_live[0] | result_live[1] |
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result_live[2] | result_live[3];
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result_live[0] = result;
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result_live[1] = result;
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result_live[2] = result;
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result_live[3] = result;
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}
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for (int c = 0; c < 4; c++) {
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if (!result_live[c] && inst->dst.writemask & (1 << c)) {
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inst->dst.writemask &= ~(1 << c);
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progress = true;
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if (inst->dst.writemask == 0) {
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if (inst->writes_accumulator || inst->writes_flag()) {
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inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type));
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} else {
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inst->opcode = BRW_OPCODE_NOP;
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break;
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}
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}
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}
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}
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}
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if (inst->dst.is_null() && inst->writes_flag()) {
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bool combined_live = false;
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for (unsigned c = 0; c < 4; c++)
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combined_live |= BITSET_TEST(flag_live, c);
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if (!combined_live) {
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inst->opcode = BRW_OPCODE_NOP;
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progress = true;
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}
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}
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if (inst->dst.file == VGRF && !inst->predicate &&
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!inst->is_align1_partial_write()) {
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for (unsigned i = 0; i < DIV_ROUND_UP(inst->size_written, 16); i++) {
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for (int c = 0; c < 4; c++) {
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if (inst->dst.writemask & (1 << c)) {
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const unsigned v = var_from_reg(alloc, inst->dst, c, i);
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BITSET_CLEAR(live, v);
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}
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}
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}
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}
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if (inst->writes_flag() && !inst->predicate) {
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for (unsigned c = 0; c < 4; c++)
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BITSET_CLEAR(flag_live, c);
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}
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if (inst->opcode == BRW_OPCODE_NOP) {
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inst->remove(block);
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continue;
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}
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for (int i = 0; i < 3; i++) {
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if (inst->src[i].file == VGRF) {
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for (unsigned j = 0; j < DIV_ROUND_UP(inst->size_read(i), 16); j++) {
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for (int c = 0; c < 4; c++) {
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const unsigned v = var_from_reg(alloc, inst->src[i], c, j);
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BITSET_SET(live, v);
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}
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}
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}
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}
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for (unsigned c = 0; c < 4; c++) {
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if (inst->reads_flag(c)) {
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BITSET_SET(flag_live, c);
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}
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}
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}
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}
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ralloc_free(live);
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ralloc_free(flag_live);
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if (progress)
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invalidate_live_intervals();
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return progress;
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}
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