AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

intel/compiler: Implement nir_intrinsic_last_invocation

Browse Source 
We haven't exposed this intrinsic as it doesn't directly correspond to
anything in SPIR-V.  However, it's used internally by some NIR passes,
namely nir_opt_uniform_atomics().

We reuse most of the infrastructure in brw_find_live_channel, but with
LZD/ADD instead of FBL.  A new SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL is
like SHADER_OPCODE_FIND_LIVE_CHANNEL but from the other side.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15484>
This commit is contained in:
Kenneth Graunke
2022-03-17 00:46:21 -07:00
committed by Marge Bot
parent af529b545a
commit 6fa66ac228
10 changed files with 57 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_fs_generator.cpp
+13 -1
View File
@@ -2425,9 +2425,21 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
prog_data) ? brw_imm_ud(~0u) :
stage == MESA_SHADER_FRAGMENT ? brw_vmask_reg() :
brw_dmask_reg();
brw_find_live_channel(p, dst, mask);
brw_find_live_channel(p, dst, mask, false);
break;
}
case SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL: {
/* ce0 doesn't consider the thread dispatch mask, so if we want
* to find the true last enabled channel, we need to apply that too.
*/
const struct brw_reg mask =
stage == MESA_SHADER_FRAGMENT ? brw_vmask_reg() : brw_dmask_reg();
brw_find_live_channel(p, dst, mask, true);
break;
}
case FS_OPCODE_LOAD_LIVE_CHANNELS: {
assert(devinfo->ver >= 8);
assert(inst->force_writemask_all && inst->group == 0);