diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 76349a8d540..49f9356d91e 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -646,6 +646,9 @@ static const char *const xe2_sampler_msg_type[] = {
    [XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_B]    = "gather4_b",
    [XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_I_C]  = "gather4_i_c",
    [XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_L_C]  = "gather4_l_c",
+   [XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L] = "gather4_po_l",
+   [XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L_C] = "gather4_po_l_c",
+   [XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_B]  = "gather4_po_b",
    [HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE] = "sample_d_c",
    [GFX9_SAMPLER_MESSAGE_SAMPLE_LZ]           = "sample_lz",
    [GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ]         = "sample_c_lz",
diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h
index 41432028743..da12d1b968b 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -351,6 +351,10 @@ enum opcode {
    SHADER_OPCODE_TG4_BIAS_LOGICAL,
    SHADER_OPCODE_TG4_OFFSET,
    SHADER_OPCODE_TG4_OFFSET_LOGICAL,
+   SHADER_OPCODE_TG4_OFFSET_LOD,
+   SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL,
+   SHADER_OPCODE_TG4_OFFSET_BIAS,
+   SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL,
    SHADER_OPCODE_SAMPLEINFO,
    SHADER_OPCODE_SAMPLEINFO_LOGICAL,
 
@@ -1504,6 +1508,9 @@ enum brw_message_target {
 #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS       29
 #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS       30
 #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS       31
+#define XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L           45
+#define XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_B           46
+#define XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L_C         55
 
 /* for GFX5 only */
 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2                   0
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 1ce40c5d161..2a000cb74a8 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -277,6 +277,8 @@ fs_inst::is_control_source(unsigned arg) const
    case SHADER_OPCODE_TG4_BIAS:
    case SHADER_OPCODE_TG4_EXPLICIT_LOD:
    case SHADER_OPCODE_TG4_IMPLICIT_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS:
    case SHADER_OPCODE_SAMPLEINFO:
       return arg == 1 || arg == 2;
 
@@ -321,6 +323,8 @@ fs_inst::is_payload(unsigned arg) const
    case SHADER_OPCODE_TG4_BIAS:
    case SHADER_OPCODE_TG4_EXPLICIT_LOD:
    case SHADER_OPCODE_TG4_IMPLICIT_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS:
    case SHADER_OPCODE_SAMPLEINFO:
       return arg == 0;
 
@@ -728,6 +732,8 @@ fs_inst::components_read(unsigned i) const
    case SHADER_OPCODE_TG4_BIAS_LOGICAL:
    case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL:
    case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL:
    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
       assert(src[TEX_LOGICAL_SRC_COORD_COMPONENTS].file == IMM &&
              src[TEX_LOGICAL_SRC_GRAD_COMPONENTS].file == IMM &&
@@ -962,6 +968,8 @@ fs_inst::size_read(int arg) const
    case SHADER_OPCODE_TG4_BIAS:
    case SHADER_OPCODE_TG4_EXPLICIT_LOD:
    case SHADER_OPCODE_TG4_IMPLICIT_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS:
    case SHADER_OPCODE_SAMPLEINFO:
       if (arg == 0 && src[0].file == VGRF)
          return mlen * REG_SIZE;
@@ -1095,6 +1103,8 @@ fs_inst::implied_mrf_writes() const
    case SHADER_OPCODE_TG4_BIAS:
    case SHADER_OPCODE_TG4_EXPLICIT_LOD:
    case SHADER_OPCODE_TG4_IMPLICIT_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS:
    case SHADER_OPCODE_TXL:
    case SHADER_OPCODE_TXS:
    case SHADER_OPCODE_LOD:
@@ -1133,6 +1143,8 @@ fs_inst::has_sampler_residency() const
    case SHADER_OPCODE_TG4_BIAS_LOGICAL:
    case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL:
    case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL:
       assert(src[TEX_LOGICAL_SRC_RESIDENCY].file == IMM);
       return src[TEX_LOGICAL_SRC_RESIDENCY].ud != 0;
    default:
diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp b/src/intel/compiler/brw_fs_copy_propagation.cpp
index 15208766835..a8a3ca7537f 100644
--- a/src/intel/compiler/brw_fs_copy_propagation.cpp
+++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
@@ -1226,6 +1226,8 @@ try_constant_propagate(const brw_compiler *compiler, fs_inst *inst,
    case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL:
    case SHADER_OPCODE_TG4_LOGICAL:
    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL:
    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
    case SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
diff --git a/src/intel/compiler/brw_fs_cse.cpp b/src/intel/compiler/brw_fs_cse.cpp
index 78c36cb5b63..31e5a1b6983 100644
--- a/src/intel/compiler/brw_fs_cse.cpp
+++ b/src/intel/compiler/brw_fs_cse.cpp
@@ -97,6 +97,8 @@ is_expression(const fs_visitor *v, const fs_inst *const inst)
    case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL:
    case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL:
    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL:
    case FS_OPCODE_PACK:
       return true;
    case SHADER_OPCODE_RCP:
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index c8867bcf06d..e3bd734e9d8 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1083,6 +1083,18 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst,
          else
             msg_type = XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_I;
          break;
+      case SHADER_OPCODE_TG4_OFFSET_BIAS:
+         assert(devinfo->ver >= 20);
+         assert(!inst->shadow_compare);
+         msg_type = XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_B;
+         break;
+      case SHADER_OPCODE_TG4_OFFSET_LOD:
+         assert(devinfo->ver >= 20);
+         if (inst->shadow_compare)
+            msg_type = XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L_C;
+         else
+            msg_type = XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L;
+         break;
       case SHADER_OPCODE_SAMPLEINFO:
          msg_type = GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
          break;
@@ -2130,6 +2142,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
       case SHADER_OPCODE_TG4_BIAS:
       case SHADER_OPCODE_TG4_EXPLICIT_LOD:
       case SHADER_OPCODE_TG4_IMPLICIT_LOD:
+      case SHADER_OPCODE_TG4_OFFSET_LOD:
+      case SHADER_OPCODE_TG4_OFFSET_BIAS:
       case SHADER_OPCODE_SAMPLEINFO:
          assert(inst->src[0].file == BAD_FILE);
          generate_tex(inst, dst, src[1], src[2]);
diff --git a/src/intel/compiler/brw_fs_lower_simd_width.cpp b/src/intel/compiler/brw_fs_lower_simd_width.cpp
index 76bf5efb166..1dedff855c0 100644
--- a/src/intel/compiler/brw_fs_lower_simd_width.cpp
+++ b/src/intel/compiler/brw_fs_lower_simd_width.cpp
@@ -553,6 +553,8 @@ brw_fs_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst)
    case SHADER_OPCODE_TG4_BIAS_LOGICAL:
    case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL:
    case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL:
       return get_sampler_lowered_simd_width(devinfo, inst);
 
    /* On gfx12 parameters are fixed to 16-bit values and therefore they all
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 1ea0359ba44..979740fef12 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -8088,6 +8088,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
    ASSERTED bool got_lod = false;
    ASSERTED bool got_bias = false;
    bool pack_lod_and_array_index = false;
+   bool pack_lod_bias_and_offset = false;
    uint32_t header_bits = 0;
    for (unsigned i = 0; i < instr->num_srcs; i++) {
       nir_src nir_src = instr->src[i].src;
@@ -8218,6 +8219,16 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
          srcs[TEX_LOGICAL_SRC_MCS] = retype(src, BRW_REGISTER_TYPE_D);
          break;
 
+      /* If this parameter is present, we are packing offset U, V and LOD/Bias
+       * into a single (32-bit) value.
+       */
+      case nir_tex_src_backend2:
+         assert(instr->op == nir_texop_tg4);
+         pack_lod_bias_and_offset = true;
+         srcs[TEX_LOGICAL_SRC_LOD] =
+            retype(get_nir_src_imm(ntb, instr->src[i].src), BRW_REGISTER_TYPE_F);
+         break;
+
       /* If this parameter is present, we are packing either the explicit LOD
        * or LOD bias and the array index into a single (32-bit) value when
        * 32-bit texture coordinates are used.
@@ -8323,6 +8334,13 @@ fs_nir_emit_texture(nir_to_brw_state &ntb,
 
             if (got_lod)
                opcode = SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL;
+
+            if (pack_lod_bias_and_offset) {
+               if (got_lod)
+                  opcode = SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL;
+               if (got_bias)
+                  opcode = SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL;
+            }
          }
       }
       break;
diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp
index f6403df7c5b..9da5104dd6a 100644
--- a/src/intel/compiler/brw_ir_performance.cpp
+++ b/src/intel/compiler/brw_ir_performance.cpp
@@ -949,6 +949,8 @@ namespace {
       case SHADER_OPCODE_TG4_EXPLICIT_LOD:
       case SHADER_OPCODE_TG4_IMPLICIT_LOD:
       case SHADER_OPCODE_TG4_OFFSET:
+      case SHADER_OPCODE_TG4_OFFSET_LOD:
+      case SHADER_OPCODE_TG4_OFFSET_BIAS:
       case SHADER_OPCODE_SAMPLEINFO:
       case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
          return calculate_desc(info, EU_UNIT_SAMPLER, 2, 0, 0, 0, 16 /* XXX */,
diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp
index 0db64708f1c..472340c3e06 100644
--- a/src/intel/compiler/brw_lower_logical_sends.cpp
+++ b/src/intel/compiler/brw_lower_logical_sends.cpp
@@ -905,6 +905,15 @@ sampler_msg_type(const intel_device_info *devinfo,
       assert(devinfo->ver >= 7);
       return shadow_compare ? GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C :
                               GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
+   case SHADER_OPCODE_TG4_OFFSET_LOD:
+      assert(!has_min_lod);
+      assert(devinfo->ver >= 20);
+      return shadow_compare ? XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L_C:
+                              XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L;
+   case SHADER_OPCODE_TG4_OFFSET_BIAS:
+      assert(!has_min_lod);
+      assert(devinfo->ver >= 20);
+      return XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_B;
    case SHADER_OPCODE_TG4_BIAS:
       assert(!has_min_lod);
       assert(devinfo->ver >= 20);
@@ -976,6 +985,8 @@ shader_opcode_needs_header(opcode op)
    switch (op) {
    case SHADER_OPCODE_TG4:
    case SHADER_OPCODE_TG4_OFFSET:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS:
+   case SHADER_OPCODE_TG4_OFFSET_LOD:
    case SHADER_OPCODE_TG4_BIAS:
    case SHADER_OPCODE_TG4_EXPLICIT_LOD:
    case SHADER_OPCODE_TG4_IMPLICIT_LOD:
@@ -1164,6 +1175,8 @@ lower_sampler_logical_send_gfx7(const fs_builder &bld, fs_inst *inst, opcode op,
    case FS_OPCODE_TXB:
    case SHADER_OPCODE_TG4_BIAS:
    case SHADER_OPCODE_TG4_EXPLICIT_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_LOD:
+   case SHADER_OPCODE_TG4_OFFSET_BIAS:
    case SHADER_OPCODE_TXL:
       bld.MOV(sources[length], lod);
       length++;
@@ -3221,6 +3234,14 @@ brw_fs_lower_logical_sends(fs_visitor &s)
          lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4_OFFSET);
          break;
 
+      case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL:
+         lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4_OFFSET_LOD);
+         break;
+
+      case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL:
+         lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_TG4_OFFSET_BIAS);
+         break;
+
       case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
          lower_sampler_logical_send(ibld, inst, SHADER_OPCODE_SAMPLEINFO);
          break;
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 21318f2c667..ed260ebe468 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -270,6 +270,14 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
       return "tg4_offset";
    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
       return "tg4_offset_logical";
+   case SHADER_OPCODE_TG4_OFFSET_LOD:
+      return "tg4_offset_lod";
+   case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL:
+      return "tg4_offset_lod_logical";
+   case SHADER_OPCODE_TG4_OFFSET_BIAS:
+      return "tg4_offset_bias";
+   case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL:
+      return "tg4_offset_bias_logical";
    case SHADER_OPCODE_TG4_BIAS:
       return "tg4_b";
    case SHADER_OPCODE_TG4_BIAS_LOGICAL: