From 6e88fa8a77b3aa130aed32664aac0ca13b41506b Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Thu, 15 Feb 2024 02:03:38 -0800 Subject: [PATCH] intel/brw: Remove Gfx8- code from brw_compile_* functions Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_compile_gs.cpp | 92 +++++++----------- src/intel/compiler/brw_compile_vs.cpp | 6 +- src/intel/compiler/brw_compiler.h | 5 - src/intel/compiler/brw_fs.cpp | 49 +--------- src/intel/compiler/brw_interpolation_map.c | 108 --------------------- src/intel/compiler/meson.build | 1 - 6 files changed, 39 insertions(+), 222 deletions(-) delete mode 100644 src/intel/compiler/brw_interpolation_map.c diff --git a/src/intel/compiler/brw_compile_gs.cpp b/src/intel/compiler/brw_compile_gs.cpp index 19728e2d5c2..5ec51e376c9 100644 --- a/src/intel/compiler/brw_compile_gs.cpp +++ b/src/intel/compiler/brw_compile_gs.cpp @@ -75,42 +75,37 @@ brw_compile_gs(const struct brw_compiler *compiler, prog_data->invocations = nir->info.gs.invocations; - if (compiler->devinfo->ver >= 8) - nir_gs_count_vertices_and_primitives( - nir, &prog_data->static_vertex_count, nullptr, nullptr, 1u); + nir_gs_count_vertices_and_primitives( + nir, &prog_data->static_vertex_count, nullptr, nullptr, 1u); - if (compiler->devinfo->ver >= 7) { - if (nir->info.gs.output_primitive == MESA_PRIM_POINTS) { - /* When the output type is points, the geometry shader may output data - * to multiple streams, and EndPrimitive() has no effect. So we - * configure the hardware to interpret the control data as stream ID. - */ - prog_data->control_data_format = GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID; + if (nir->info.gs.output_primitive == MESA_PRIM_POINTS) { + /* When the output type is points, the geometry shader may output data + * to multiple streams, and EndPrimitive() has no effect. So we + * configure the hardware to interpret the control data as stream ID. + */ + prog_data->control_data_format = GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID; - /* We only have to emit control bits if we are using non-zero streams */ - if (nir->info.gs.active_stream_mask != (1 << 0)) - c.control_data_bits_per_vertex = 2; - else - c.control_data_bits_per_vertex = 0; - } else { - /* When the output type is triangle_strip or line_strip, EndPrimitive() - * may be used to terminate the current strip and start a new one - * (similar to primitive restart), and outputting data to multiple - * streams is not supported. So we configure the hardware to interpret - * the control data as EndPrimitive information (a.k.a. "cut bits"). - */ - prog_data->control_data_format = GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT; - - /* We only need to output control data if the shader actually calls - * EndPrimitive(). - */ - c.control_data_bits_per_vertex = - nir->info.gs.uses_end_primitive ? 1 : 0; - } + /* We only have to emit control bits if we are using non-zero streams */ + if (nir->info.gs.active_stream_mask != (1 << 0)) + c.control_data_bits_per_vertex = 2; + else + c.control_data_bits_per_vertex = 0; } else { - /* There are no control data bits in gfx6. */ - c.control_data_bits_per_vertex = 0; + /* When the output type is triangle_strip or line_strip, EndPrimitive() + * may be used to terminate the current strip and start a new one + * (similar to primitive restart), and outputting data to multiple + * streams is not supported. So we configure the hardware to interpret + * the control data as EndPrimitive information (a.k.a. "cut bits"). + */ + prog_data->control_data_format = GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT; + + /* We only need to output control data if the shader actually calls + * EndPrimitive(). + */ + c.control_data_bits_per_vertex = + nir->info.gs.uses_end_primitive ? 1 : 0; } + c.control_data_header_size_bits = nir->info.gs.vertices_out * c.control_data_bits_per_vertex; @@ -167,8 +162,7 @@ brw_compile_gs(const struct brw_compiler *compiler, * */ unsigned output_vertex_size_bytes = prog_data->base.vue_map.num_slots * 16; - assert(compiler->devinfo->ver == 6 || - output_vertex_size_bytes <= GFX7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES); + assert(output_vertex_size_bytes <= GFX7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES); prog_data->output_vertex_size_hwords = ALIGN(output_vertex_size_bytes, 32) / 32; @@ -200,24 +194,16 @@ brw_compile_gs(const struct brw_compiler *compiler, * we need, and if it's too large, fail to compile. * * The above is for gfx7+ where we have a single URB entry that will hold - * all the output. In gfx6, we will have to allocate URB entries for every - * vertex we emit, so our URB entries only need to be large enough to hold - * a single vertex. Also, gfx6 does not have a control data header. + * all the output. */ - unsigned output_size_bytes; - if (compiler->devinfo->ver >= 7) { - output_size_bytes = - prog_data->output_vertex_size_hwords * 32 * nir->info.gs.vertices_out; - output_size_bytes += 32 * prog_data->control_data_header_size_hwords; - } else { - output_size_bytes = prog_data->output_vertex_size_hwords * 32; - } + unsigned output_size_bytes = + prog_data->output_vertex_size_hwords * 32 * nir->info.gs.vertices_out; + output_size_bytes += 32 * prog_data->control_data_header_size_hwords; /* Broadwell stores "Vertex Count" as a full 8 DWord (32 byte) URB output, * which comes before the control header. */ - if (compiler->devinfo->ver >= 8) - output_size_bytes += 32; + output_size_bytes += 32; /* Shaders can technically set max_vertices = 0, at which point we * may have a URB size of 0 bytes. Nothing good can come from that, @@ -227,20 +213,12 @@ brw_compile_gs(const struct brw_compiler *compiler, output_size_bytes = 1; unsigned max_output_size_bytes = GFX7_MAX_GS_URB_ENTRY_SIZE_BYTES; - if (compiler->devinfo->ver == 6) - max_output_size_bytes = GFX6_MAX_GS_URB_ENTRY_SIZE_BYTES; if (output_size_bytes > max_output_size_bytes) return NULL; - /* URB entry sizes are stored as a multiple of 64 bytes in gfx7+ and - * a multiple of 128 bytes in gfx6. - */ - if (compiler->devinfo->ver >= 7) { - prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64; - } else { - prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 128) / 128; - } + /* URB entry sizes are stored as a multiple of 64 bytes in gfx7+. */ + prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64; assert(nir->info.gs.output_primitive < ARRAY_SIZE(gl_prim_to_hw_prim)); prog_data->output_topology = diff --git a/src/intel/compiler/brw_compile_vs.cpp b/src/intel/compiler/brw_compile_vs.cpp index 983c2a837ec..e3558597f0f 100644 --- a/src/intel/compiler/brw_compile_vs.cpp +++ b/src/intel/compiler/brw_compile_vs.cpp @@ -88,11 +88,7 @@ brw_compile_vs(const struct brw_compiler *compiler, const unsigned vue_entries = MAX2(nr_attribute_slots, (unsigned)prog_data->base.vue_map.num_slots); - if (compiler->devinfo->ver == 6) { - prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 8); - } else { - prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4); - } + prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4); if (unlikely(debug_enabled)) { fprintf(stderr, "VS Output "); diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 765a6cb3416..aba1afe4648 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -1266,11 +1266,6 @@ void brw_compute_tess_vue_map(struct intel_vue_map *const vue_map, uint64_t slots_valid, uint32_t is_patch); -/* brw_interpolation_map.c */ -void brw_setup_vue_interpolation(const struct intel_vue_map *vue_map, - struct nir_shader *nir, - struct brw_wm_prog_data *prog_data); - struct brw_vue_prog_data { struct brw_stage_prog_data base; struct intel_vue_map vue_map; diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 2a33b8e5fa2..2806ce9b6d8 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -3667,20 +3667,17 @@ brw_compile_fs(const struct brw_compiler *compiler, prog_data->base.total_scratch = 0; const struct intel_device_info *devinfo = compiler->devinfo; - const unsigned max_subgroup_size = compiler->devinfo->ver >= 6 ? 32 : 16; + const unsigned max_subgroup_size = 32; brw_nir_apply_key(nir, compiler, &key->base, max_subgroup_size); brw_nir_lower_fs_inputs(nir, devinfo, key); brw_nir_lower_fs_outputs(nir); - if (devinfo->ver < 6) - brw_setup_vue_interpolation(params->vue_map, nir, prog_data); - /* From the SKL PRM, Volume 7, "Alpha Coverage": * "If Pixel Shader outputs oMask, AlphaToCoverage is disabled in * hardware, regardless of the state setting for this feature." */ - if (devinfo->ver > 6 && key->alpha_to_coverage != BRW_NEVER) { + if (key->alpha_to_coverage != BRW_NEVER) { /* Run constant fold optimization in order to get the correct source * offset to determine render target 0 store instruction in * emit_alpha_to_coverage pass. @@ -3725,16 +3722,6 @@ brw_compile_fs(const struct brw_compiler *compiler, } } - /* Limit dispatch width to simd8 with dual source blending on gfx8. - * See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1917 - */ - if (devinfo->ver == 8 && prog_data->dual_src_blend && - INTEL_SIMD(FS, 8)) { - assert(!params->use_rep_send); - v8->limit_dispatch_width(8, "gfx8 workaround: " - "using SIMD8 when dual src blending.\n"); - } - if (key->coarse_pixel && devinfo->ver < 20) { if (prog_data->dual_src_blend) { v8->limit_dispatch_width(8, "SIMD16 coarse pixel shading cannot" @@ -3781,7 +3768,7 @@ brw_compile_fs(const struct brw_compiler *compiler, if (!has_spilled && (!v8 || v8->max_dispatch_width >= 32) && (!v16 || v16->max_dispatch_width >= 32) && !params->use_rep_send && - devinfo->ver >= 6 && !simd16_failed && + !simd16_failed && INTEL_SIMD(FS, 32)) { /* Try a SIMD32 compile */ v32 = std::make_unique(compiler, ¶ms->base, key, @@ -3891,36 +3878,6 @@ brw_compile_fs(const struct brw_compiler *compiler, if (params->use_rep_send) simd8_cfg = NULL; - /* Prior to Iron Lake, the PS had a single shader offset with a jump table - * at the top to select the shader. We've never implemented that. - * Instead, we just give them exactly one shader and we pick the widest one - * available. - */ - if (compiler->devinfo->ver < 5) { - if (simd32_cfg || simd16_cfg) - simd8_cfg = NULL; - if (simd32_cfg) - simd16_cfg = NULL; - } - - /* If computed depth is enabled SNB only allows SIMD8. */ - if (compiler->devinfo->ver == 6 && - prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF) - assert(simd16_cfg == NULL && simd32_cfg == NULL); - - if (compiler->devinfo->ver <= 5 && !simd8_cfg) { - /* Iron lake and earlier only have one Dispatch GRF start field. Make - * the data available in the base prog data struct for convenience. - */ - if (simd16_cfg) { - prog_data->base.dispatch_grf_start_reg = - prog_data->dispatch_grf_start_reg_16; - } else if (simd32_cfg) { - prog_data->base.dispatch_grf_start_reg = - prog_data->dispatch_grf_start_reg_32; - } - } - fs_generator g(compiler, ¶ms->base, &prog_data->base, v8 && v8->runtime_check_aads_emit, MESA_SHADER_FRAGMENT); diff --git a/src/intel/compiler/brw_interpolation_map.c b/src/intel/compiler/brw_interpolation_map.c deleted file mode 100644 index bdda1ad5d48..00000000000 --- a/src/intel/compiler/brw_interpolation_map.c +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright © 2013 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "brw_compiler.h" -#include "compiler/nir/nir.h" - -static char const *get_qual_name(int mode) -{ - switch (mode) { - case INTERP_MODE_NONE: return "none"; - case INTERP_MODE_FLAT: return "flat"; - case INTERP_MODE_SMOOTH: return "smooth"; - case INTERP_MODE_NOPERSPECTIVE: return "nopersp"; - default: return "???"; - } -} - -static void -gfx4_frag_prog_set_interp_modes(struct brw_wm_prog_data *prog_data, - const struct intel_vue_map *vue_map, - unsigned location, unsigned slot_count, - enum glsl_interp_mode interp) -{ - for (unsigned k = 0; k < slot_count; k++) { - unsigned slot = vue_map->varying_to_slot[location + k]; - if (slot != -1 && prog_data->interp_mode[slot] == INTERP_MODE_NONE) { - prog_data->interp_mode[slot] = interp; - - if (prog_data->interp_mode[slot] == INTERP_MODE_FLAT) { - prog_data->contains_flat_varying = true; - } else if (prog_data->interp_mode[slot] == INTERP_MODE_NOPERSPECTIVE) { - prog_data->contains_noperspective_varying = true; - } - } - } -} - -/* Set up interpolation modes for every element in the VUE */ -void -brw_setup_vue_interpolation(const struct intel_vue_map *vue_map, nir_shader *nir, - struct brw_wm_prog_data *prog_data) -{ - /* Initialise interp_mode. INTERP_MODE_NONE == 0 */ - memset(prog_data->interp_mode, 0, sizeof(prog_data->interp_mode)); - - if (!vue_map) - return; - - /* HPOS always wants noperspective. setting it up here allows - * us to not need special handling in the SF program. - */ - unsigned pos_slot = vue_map->varying_to_slot[VARYING_SLOT_POS]; - if (pos_slot != -1) {; - prog_data->interp_mode[pos_slot] = INTERP_MODE_NOPERSPECTIVE; - prog_data->contains_noperspective_varying = true; - } - - nir_foreach_shader_in_variable(var, nir) { - unsigned location = var->data.location; - unsigned slot_count = glsl_count_attribute_slots(var->type, false); - - gfx4_frag_prog_set_interp_modes(prog_data, vue_map, location, slot_count, - var->data.interpolation); - - if (location == VARYING_SLOT_COL0 || location == VARYING_SLOT_COL1) { - location = location + VARYING_SLOT_BFC0 - VARYING_SLOT_COL0; - gfx4_frag_prog_set_interp_modes(prog_data, vue_map, location, - slot_count, var->data.interpolation); - } - } - - const bool debug = false; - if (debug) { - fprintf(stderr, "VUE map:\n"); - for (int i = 0; i < vue_map->num_slots; i++) { - int varying = vue_map->slot_to_varying[i]; - if (varying == -1) { - fprintf(stderr, "%d: --\n", i); - continue; - } - - fprintf(stderr, "%d: %d %s ofs %d\n", - i, varying, - get_qual_name(prog_data->interp_mode[i]), - brw_vue_slot_to_offset(i)); - } - } -} diff --git a/src/intel/compiler/meson.build b/src/intel/compiler/meson.build index 6a55f59568c..1666844159c 100644 --- a/src/intel/compiler/meson.build +++ b/src/intel/compiler/meson.build @@ -89,7 +89,6 @@ libintel_compiler_brw_files = files( 'brw_fs_visitor.cpp', 'brw_fs_workaround.cpp', 'brw_inst.h', - 'brw_interpolation_map.c', 'brw_ir.h', 'brw_ir_allocator.h', 'brw_ir_analysis.h',