diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h index f0a4e0a3a16..5653a1c036a 100644 --- a/include/drm-uapi/xe_drm.h +++ b/include/drm-uapi/xe_drm.h @@ -735,6 +735,7 @@ struct drm_xe_device_query { #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7 #define DRM_XE_DEVICE_QUERY_OA_UNITS 8 #define DRM_XE_DEVICE_QUERY_PXP_STATUS 9 +#define DRM_XE_DEVICE_QUERY_EU_STALL 10 /** @query: The type of data to query */ __u32 query; @@ -1496,6 +1497,7 @@ struct drm_xe_wait_user_fence { enum drm_xe_observation_type { /** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */ DRM_XE_OBSERVATION_TYPE_OA, + DRM_XE_OBSERVATION_TYPE_EU_STALL, }; /** @@ -1848,6 +1850,132 @@ enum drm_xe_pxp_session_type { /* ID of the protected content session managed by Xe when PXP is active */ #define DRM_XE_PXP_HWDRM_DEFAULT_SESSION 0xf +enum drm_xe_eu_stall_property_id { +#define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY 0 + /** + * @DRM_XE_EU_STALL_PROP_GT_ID: GT ID of the GT on which + * EU stall data will be captured. + */ + DRM_XE_EU_STALL_PROP_GT_ID = 1, + + /** + * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate + * in GPU cycles. For example: + * 251, 251x2, 251x3, 251x4, 251x5, 251x6 and 251x7. + */ + DRM_XE_EU_STALL_PROP_SAMPLE_RATE, + + /** + * @DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS: Minimum number of + * EU stall data reports to be present in the kernel buffer + * before unblocking poll or read that is blocked. + */ + DRM_XE_EU_STALL_PROP_WAIT_NUM_REPORTS, + + DRM_XE_EU_STALL_PROP_MAX +}; + +/** + * struct drm_xe_query_eu_stall - Information about EU stall sampling. + * + * If a query is made with a struct @drm_xe_device_query where .query + * is equal to @DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses + * struct @drm_xe_query_eu_stall in .data. + */ +struct drm_xe_query_eu_stall { + /** @extensions: Pointer to the first extension struct, if any */ + __u64 extensions; + + /** @capabilities: EU stall capabilities bit-mask */ + __u64 capabilities; + + /** @record_size: size of each EU stall data record */ + __u64 record_size; + + /** @per_xecore_buf_size: Per XeCore buffer size */ + __u64 per_xecore_buf_size; + + /** @reserved: Reserved */ + __u64 reserved[5]; + + /** @num_sampling_rates: Number of sampling rates supported */ + __u64 num_sampling_rates; + + /** + * @sampling_rates: Flexible array of sampling rates + * sorted in the fastest to slowest order. + * Sampling rates are specified in GPU clock cycles. + */ + __u64 sampling_rates[]; +}; +#define DRM_XE_EU_STALL_CAPS_BASE (1 << 0) + +/** + * struct drm_xe_eu_stall_data_pvc - EU stall data format for PVC + * + * Bits Field + * 0 to 28 IP (addr) + * 29 to 36 active count + * 37 to 44 other count + * 45 to 52 control count + * 53 to 60 pipestall count + * 61 to 68 send count + * 69 to 76 dist_acc count + * 77 to 84 sbid count + * 85 to 92 sync count + * 93 to 100 inst_fetch count + */ +struct drm_xe_eu_stall_data_pvc { + __u64 ip_addr:29; + __u64 active_count:8; + __u64 other_count:8; + __u64 control_count:8; + __u64 pipestall_count:8; + __u64 send_count:8; + __u64 dist_acc_count:8; + __u64 sbid_count:8; + __u64 sync_count:8; + __u64 inst_fetch_count:8; + __u64 unused_bits:27; + __u64 unused[6]; +} __attribute__((packed)); + +/** + * struct drm_xe_eu_stall_data_xe2 - EU stall data format for LNL, BMG + * + * Bits Field + * 0 to 28 IP (addr) + * 29 to 36 Tdr count + * 37 to 44 other count + * 45 to 52 control count + * 53 to 60 pipestall count + * 61 to 68 send count + * 69 to 76 dist_acc count + * 77 to 84 sbid count + * 85 to 92 sync count + * 93 to 100 inst_fetch count + * 101 to 108 Active count + * 109 to 111 Exid + * 112 EndFlag (is always 1) + */ +struct drm_xe_eu_stall_data_xe2 { + __u64 ip_addr:29; + __u64 tdr_count:8; + __u64 other_count:8; + __u64 control_count:8; + __u64 pipestall_count:8; + __u64 send_count:8; + __u64 dist_acc_count:8; + __u64 sbid_count:8; + __u64 sync_count:8; + __u64 inst_fetch_count:8; + __u64 active_count:8; + __u64 ex_id:3; + __u64 end_flag:1; + __u64 unused_bits:15; + __u64 unused[6]; +} __attribute__((packed)); + #if defined(__cplusplus) } #endif