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i915tex: Wait for pending scheduled flips before switching vsync pipe.

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This avoids hangs when the vblank sequence numbers are not in sync between
pipes, in particular when they run at different refresh rates.
This commit is contained in:
Michel Dänzer
2007-03-09 20:00:13 +01:00
parent bb0760ca4f
commit 6e0878becf
1 changed files with 19 additions and 0 deletions
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src/mesa/drivers/dri/i915tex/intel_buffers.c
+19
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@@ -300,8 +300,27 @@ intelWindowMoved(struct intel_context *intel)
}
if (flags != intel_fb->vblank_flags) {
drmVBlank vbl;
int i;
vbl.request.type = DRM_VBLANK_ABSOLUTE;
if ( intel_fb->vblank_flags & VBLANK_FLAG_SECONDARY ) {
vbl.request.type |= DRM_VBLANK_SECONDARY;
}
for (i = 0; i < intel_fb->pf_num_pages; i++) {
vbl.request.sequence = intel_fb->color_rb[i]->vbl_pending;
drmWaitVBlank(intel->driFd, &vbl);
}
intel_fb->vblank_flags = flags;
driGetCurrentVBlank(dPriv, intel_fb->vblank_flags, &intel_fb->vbl_seq);
intel_fb->vbl_waited = intel_fb->vbl_seq;
for (i = 0; i < intel_fb->pf_num_pages; i++) {
intel_fb->color_rb[i]->vbl_pending = intel_fb->vbl_waited;
}
}
} else {
intel_fb->vblank_flags &= ~VBLANK_FLAG_SECONDARY;