diff --git a/src/amd/common/ac_vcn_enc.h b/src/amd/common/ac_vcn_enc.h
index 97a614c8a65..86afe3fdf54 100644
--- a/src/amd/common/ac_vcn_enc.h
+++ b/src/amd/common/ac_vcn_enc.h
@@ -133,6 +133,9 @@
 #define RENCODE_AV1_CDEF_ALGORITHM_FRAME_CONTEXT_SIZE                               (64 * 8 * 3)
 #define RENCODE_AV1_CDEF_MAX_NUM                                                    8
 #define RENCODE_MAX_METADATA_BUFFER_SIZE_PER_FRAME                                  1024
+#define RENCODE_AV1_MAX_TILE_COLS                                                   64
+#define RENCODE_AV1_MAX_TILE_ROWS                                                   64
+#define RENCODE_AV1_MAX_TILE_AREA                                                   (4096 * 2304)
 #define RENCODE_INVALID_COLOC_OFFSET                                                0XFFFFFFFF
 
 #define RENCODE_PICTURE_TYPE_B                                                      0
@@ -300,17 +303,18 @@ typedef struct rvcn_enc_av1_spec_misc_s {
    uint32_t disable_frame_end_update_cdf;
    uint32_t num_tiles_per_picture;
    /* for vcn5 */
+   bool separate_delta_q;
    uint32_t cdef_bits;
    uint32_t cdef_damping_minus3;
    uint32_t cdef_y_pri_strength[RENCODE_AV1_CDEF_MAX_NUM];
    uint32_t cdef_y_sec_strength[RENCODE_AV1_CDEF_MAX_NUM];
    uint32_t cdef_uv_pri_strength[RENCODE_AV1_CDEF_MAX_NUM];
    uint32_t cdef_uv_sec_strength[RENCODE_AV1_CDEF_MAX_NUM];
-   uint32_t delta_q_y_dc;
-   uint32_t delta_q_u_dc;
-   uint32_t delta_q_u_ac;
-   uint32_t delta_q_v_dc;
-   uint32_t delta_q_v_ac;
+    int32_t delta_q_y_dc;
+    int32_t delta_q_u_dc;
+    int32_t delta_q_u_ac;
+    int32_t delta_q_v_dc;
+    int32_t delta_q_v_ac;
 } rvcn_enc_av1_spec_misc_t;
 
 /* vcn5 */
@@ -319,11 +323,16 @@ typedef struct rvcn_enc_av1_tile_group_s {
    uint32_t end;
 } rvcn_enc_av1_tile_group_t;
 
-#define RENCODE_AV1_TILE_CONFIG_MAX_NUM_COLS            2
-#define RENCODE_AV1_TILE_CONFIG_MAX_NUM_ROWS            16
-#define RENCODE_AV1_CONTEXT_UPDATE_TILE_ID_MODE_DEFAULT 2
+#define RENCODE_AV1_TILE_CONFIG_MAX_NUM_COLS               2
+#define RENCODE_AV1_TILE_CONFIG_MAX_NUM_ROWS               16
+#define RENCODE_AV1_CONTEXT_UPDATE_TILE_ID_MODE_CUSTOMIZED 1
+#define RENCODE_AV1_CONTEXT_UPDATE_TILE_ID_MODE_DEFAULT    2
 /* vcn5 */
 typedef struct rvcn_enc_av1_tile_config_s {
+   /* check if app settings can be applied or not, due to some
+    * constraints, the settings only meet the limitations can
+    * be used, then all the app settings can be applied.*/
+   bool     apply_app_setting;
    bool     uniform_tile_spacing;
    uint32_t num_tile_cols;
    uint32_t num_tile_rows;
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
index 8facdc4d24b..ff174d3f9ff 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.c
@@ -16,8 +16,6 @@
 #include "util/u_video.h"
 #include "vl/vl_video_buffer.h"
 
-#include <stdio.h>
-
 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
 
 /* set quality modes from the input */
@@ -1692,6 +1690,30 @@ void radeon_enc_code_se(struct radeon_encoder *enc, int value)
    radeon_enc_code_ue(enc, v);
 }
 
+void radeon_enc_code_ns(struct radeon_encoder *enc, unsigned int value, unsigned int max)
+{
+   unsigned w = 0;
+   unsigned m;
+   unsigned max_num = max;
+
+   while ( max_num ) {
+      max_num >>= 1;
+      w++;
+   }
+
+   m = ( 1 << w ) - max;
+
+   assert(w > 1);
+
+   if ( value < m )
+      radeon_enc_code_fixed_bits(enc, value, (w - 1));
+   else {
+      unsigned diff = value - m;
+      unsigned out = (((diff >> 1) + m) << 1) | (diff & 0x1);
+      radeon_enc_code_fixed_bits(enc, out, w);
+   }
+}
+
 /* dummy function for re-using the same pipeline */
 void radeon_enc_dummy(struct radeon_encoder *enc) {}
 
diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_enc.h b/src/gallium/drivers/radeonsi/radeon_vcn_enc.h
index 5a94f41285c..b50ecdde0e2 100644
--- a/src/gallium/drivers/radeonsi/radeon_vcn_enc.h
+++ b/src/gallium/drivers/radeonsi/radeon_vcn_enc.h
@@ -108,6 +108,7 @@ struct radeon_enc_pic {
    bool pcm_enabled_flag;
    bool sps_temporal_mvp_enabled_flag;
    bool use_rc_per_pic_ex;
+   bool av1_tile_spliting_legacy_flag;
 
    struct {
       struct {
@@ -126,6 +127,7 @@ struct radeon_enc_pic {
             uint32_t stream_obu_frame:1;  /* all frames have the same number of tiles */
             uint32_t need_av1_seq:1;
             uint32_t av1_mark_long_term_reference:1;
+            uint32_t tile_config_flag:1;
          };
          uint32_t render_width;
          uint32_t render_height;
@@ -290,6 +292,23 @@ struct radeon_encoder {
    struct pipe_context *ectx;
 };
 
+
+/* structure for determining av1 tile division scheme.
+ * In one direction, it is trying to split width/height into two parts,
+ * main and  border, each of which has a length (number of sbs),
+ * Therefore, it has two possible tile sizes, even with multiple
+ * tiles, and in non-uniformed case, it is trying to make tile sizes
+ * as similar as possible.
+ */
+
+struct tile_1d_layout {
+   bool     uniform_tile_flag;
+   uint32_t nb_main_sb;     /* if non-uniform, it means the first part */
+   uint32_t nb_border_sb;   /* if non-uniform, it means the second part */
+   uint32_t nb_main_tile;
+   uint32_t nb_border_tile;
+};
+
 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer_lean *buf,
                            unsigned usage, enum radeon_bo_domain domain, signed offset);
 
@@ -319,6 +338,9 @@ void radeon_enc_code_uvlc(struct radeon_encoder *enc, unsigned int value);
 void radeon_enc_code_leb128(unsigned char *buf, unsigned int value,
                             unsigned int num_bytes);
 
+void radeon_enc_code_ns(struct radeon_encoder *enc, unsigned int value,
+                        unsigned int max);
+
 void radeon_enc_1_2_init(struct radeon_encoder *enc);
 
 void radeon_enc_2_0_init(struct radeon_encoder *enc);