diff --git a/src/amd/vulkan/radv_pipeline_compute.c b/src/amd/vulkan/radv_pipeline_compute.c
index 68a4e6eeecd..7fe48f9716d 100644
--- a/src/amd/vulkan/radv_pipeline_compute.c
+++ b/src/amd/vulkan/radv_pipeline_compute.c
@@ -72,6 +72,44 @@ radv_get_compute_resource_limits(const struct radv_physical_device *pdevice, con
                                          threadgroups_per_cu);
 }
 
+void
+radv_get_compute_pipeline_metadata(const struct radv_device *device, const struct radv_compute_pipeline *pipeline,
+                                   struct radv_compute_pipeline_metadata *metadata)
+{
+   const struct radv_shader *cs = pipeline->base.shaders[MESA_SHADER_COMPUTE];
+   uint32_t upload_sgpr = 0, inline_sgpr = 0;
+
+   memset(metadata, 0, sizeof(*metadata));
+
+   metadata->shader_va = radv_shader_get_va(cs) >> 8;
+   metadata->rsrc1 = cs->config.rsrc1;
+   metadata->rsrc2 = cs->config.rsrc2;
+   metadata->rsrc3 = cs->config.rsrc3;
+   metadata->compute_resource_limits = radv_get_compute_resource_limits(device->physical_device, cs);
+   metadata->block_size_x = cs->info.cs.block_size[0];
+   metadata->block_size_y = cs->info.cs.block_size[1];
+   metadata->block_size_z = cs->info.cs.block_size[2];
+   metadata->wave32 = cs->info.wave_size == 32;
+
+   const struct radv_userdata_info *grid_size_loc = radv_get_user_sgpr(cs, AC_UD_CS_GRID_SIZE);
+   if (grid_size_loc->sgpr_idx != -1) {
+      metadata->grid_base_sgpr = (cs->info.user_data_0 + 4 * grid_size_loc->sgpr_idx - SI_SH_REG_OFFSET) >> 2;
+   }
+
+   const struct radv_userdata_info *push_constant_loc = radv_get_user_sgpr(cs, AC_UD_PUSH_CONSTANTS);
+   if (push_constant_loc->sgpr_idx != -1) {
+      upload_sgpr = (cs->info.user_data_0 + 4 * push_constant_loc->sgpr_idx - SI_SH_REG_OFFSET) >> 2;
+   }
+
+   const struct radv_userdata_info *inline_push_constant_loc = radv_get_user_sgpr(cs, AC_UD_INLINE_PUSH_CONSTANTS);
+   if (inline_push_constant_loc->sgpr_idx != -1) {
+      inline_sgpr = (cs->info.user_data_0 + 4 * inline_push_constant_loc->sgpr_idx - SI_SH_REG_OFFSET) >> 2;
+   }
+
+   metadata->push_const_sgpr = upload_sgpr | (inline_sgpr << 16);
+   metadata->inline_push_const_mask = cs->info.inline_push_constant_mask;
+}
+
 void
 radv_emit_compute_shader(const struct radv_physical_device *pdevice, struct radeon_cmdbuf *cs,
                          const struct radv_shader *shader)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index dc270cd4f04..42d5e5aeac8 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -3771,6 +3771,24 @@ radv_uses_image_float32_atomics(const struct radv_device *device)
 
 bool radv_device_fault_detection_enabled(const struct radv_device *device);
 
+struct radv_compute_pipeline_metadata {
+   uint32_t shader_va;
+   uint32_t rsrc1;
+   uint32_t rsrc2;
+   uint32_t rsrc3;
+   uint32_t compute_resource_limits;
+   uint32_t block_size_x;
+   uint32_t block_size_y;
+   uint32_t block_size_z;
+   uint32_t wave32;
+   uint32_t grid_base_sgpr;
+   uint32_t push_const_sgpr;
+   uint64_t inline_push_const_mask;
+};
+
+void radv_get_compute_pipeline_metadata(const struct radv_device *device, const struct radv_compute_pipeline *pipeline,
+                                        struct radv_compute_pipeline_metadata *metadata);
+
 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) VK_FROM_HANDLE(__radv_type, __name, __handle)
 
 VK_DEFINE_HANDLE_CASTS(radv_cmd_buffer, vk.base, VkCommandBuffer, VK_OBJECT_TYPE_COMMAND_BUFFER)