From 6c8782c135cdc02b91e5c3899dce097650f756fb Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Mon, 20 Dec 2021 14:33:45 -0800 Subject: [PATCH] intel/fs: Perform 64-bit SEL_EXEC lowering in the lower_regioning pass. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/compiler/brw_fs_generator.cpp | 25 +++++-------------- src/intel/compiler/brw_fs_lower_regioning.cpp | 9 +++++++ 2 files changed, 15 insertions(+), 19 deletions(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 936da06576e..339c8c6265b 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2447,25 +2447,12 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width, case SHADER_OPCODE_SEL_EXEC: assert(inst->force_writemask_all); - if (type_sz(dst.type) > 4 && !devinfo->has_64bit_float) { - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 0), - subscript(src[1], BRW_REGISTER_TYPE_UD, 0)); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 1), - subscript(src[1], BRW_REGISTER_TYPE_UD, 1)); - brw_set_default_mask_control(p, BRW_MASK_ENABLE); - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 0), - subscript(src[0], BRW_REGISTER_TYPE_UD, 0)); - brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_UD, 1), - subscript(src[0], BRW_REGISTER_TYPE_UD, 1)); - } else { - brw_set_default_mask_control(p, BRW_MASK_DISABLE); - brw_MOV(p, dst, src[1]); - brw_set_default_mask_control(p, BRW_MASK_ENABLE); - brw_set_default_swsb(p, tgl_swsb_null()); - brw_MOV(p, dst, src[0]); - } + assert(devinfo->has_64bit_float || type_sz(dst.type) <= 4); + brw_set_default_mask_control(p, BRW_MASK_DISABLE); + brw_MOV(p, dst, src[1]); + brw_set_default_mask_control(p, BRW_MASK_ENABLE); + brw_set_default_swsb(p, tgl_swsb_null()); + brw_MOV(p, dst, src[0]); break; case SHADER_OPCODE_QUAD_SWIZZLE: diff --git a/src/intel/compiler/brw_fs_lower_regioning.cpp b/src/intel/compiler/brw_fs_lower_regioning.cpp index ff418283458..53110ef009d 100644 --- a/src/intel/compiler/brw_fs_lower_regioning.cpp +++ b/src/intel/compiler/brw_fs_lower_regioning.cpp @@ -154,6 +154,12 @@ namespace { else return t; + case SHADER_OPCODE_SEL_EXEC: + if (!has_64bit && type_sz(t) > 4) + return BRW_REGISTER_TYPE_UD; + else + return t; + case SHADER_OPCODE_QUAD_SWIZZLE: if (has_dst_aligned_region_restriction(devinfo, inst)) return brw_int_type(type_sz(t), false); @@ -260,6 +266,9 @@ namespace { case SHADER_OPCODE_MOV_INDIRECT: return 0x1; + case SHADER_OPCODE_SEL_EXEC: + return 0x3; + default: unreachable("Unknown invalid execution type source mask."); }