diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 124d9237248..54914551ca3 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -981,11 +981,8 @@ blorp_can_hiz_clear_depth(const struct intel_device_info *devinfo,
                              (max_x1_y1 ? haligned_x1 % 16 || valigned_y1 % 8 :
                               x1 % 16 || y1 % 8);
       const bool partial_clear = x0 > 0 || y0 > 0 || !max_x1_y1;
-      const bool multislice_surf = surf->levels > 1 ||
-                                   surf->logical_level0_px.depth > 1 ||
-                                   surf->logical_level0_px.array_len > 1;
 
-      if (unaligned && (partial_clear || multislice_surf))
+      if (unaligned && (partial_clear || surf->levels > 1))
          return false;
    }
 
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index 33a9e5fd5bb..7fea1e2ab83 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1862,6 +1862,21 @@ isl_calc_array_pitch_el_rows_gfx4_2d(
       pitch_el_rows = isl_align(pitch_el_rows, tile_info->logical_extent_el.height);
    }
 
+   if (isl_surf_usage_is_depth(info->usage) &&
+       _isl_surf_info_supports_ccs(dev, info->format, info->usage)) {
+      /* From the TGL PRM, Vol 9, "Compressed Depth Buffers" (under the
+       * "Texture performant" and "ZCS" columns):
+       *
+       *    Update with clear at either 16x8 or 8x4 granularity, based on
+       *    fs_clr or otherwise.
+       *
+       * When fast-clearing, hardware behaves in unexpected ways if the clear
+       * rectangle, aligned to 16x8, could cover neighboring LODs. Align the
+       * array pitch to 8 in order to increase the number of aligned LODs.
+       */
+      pitch_el_rows = isl_align(pitch_el_rows, 8);
+   }
+
    return pitch_el_rows;
 }