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etnaviv: don't enable RT full-overwrite when logicop is enabled

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Logicop is a form of blending with the framebuffer, so we must allow
framebuffer reads when logicop is enabled.

Fixes: piglit gl-1.0-logicop on GC3000, which has logicop support

Signed-off-by: Lucas Stach <dev@lynxeye.de>
This commit is contained in:
Lucas Stach
2017-07-12 22:49:09 +02:00
parent 7567e3ece8
commit 6ace0b8bc8
2 changed files with 14 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/etnaviv/etnaviv_blend.c
+13 -5
View File
@@ -35,8 +35,10 @@ void *
etna_blend_state_create(struct pipe_context *pctx, etna_blend_state_create(struct pipe_context *pctx,
const struct pipe_blend_state *so) const struct pipe_blend_state *so)
{ {
struct etna_context *ctx = etna_context(pctx);
const struct pipe_rt_blend_state *rt0 = &so->rt[0]; const struct pipe_rt_blend_state *rt0 = &so->rt[0];
struct etna_blend_state *co = CALLOC_STRUCT(etna_blend_state); struct etna_blend_state *co = CALLOC_STRUCT(etna_blend_state);
bool alpha_enable, logicop_enable;
if (!co) if (!co)
return NULL; return NULL;
@@ -48,7 +50,7 @@ etna_blend_state_create(struct pipe_context *pctx,
* - NOT source factor is ONE and destination factor ZERO for both rgb and * - NOT source factor is ONE and destination factor ZERO for both rgb and
* alpha (which would mean that blending is effectively disabled) * alpha (which would mean that blending is effectively disabled)
*/ */
co->enable = rt0->blend_enable && alpha_enable = rt0->blend_enable &&
!(rt0->rgb_src_factor == PIPE_BLENDFACTOR_ONE && !(rt0->rgb_src_factor == PIPE_BLENDFACTOR_ONE &&
rt0->rgb_dst_factor == PIPE_BLENDFACTOR_ZERO && rt0->rgb_dst_factor == PIPE_BLENDFACTOR_ZERO &&
rt0->alpha_src_factor == PIPE_BLENDFACTOR_ONE && rt0->alpha_src_factor == PIPE_BLENDFACTOR_ONE &&
@@ -59,11 +61,11 @@ etna_blend_state_create(struct pipe_context *pctx,
* - NOT source factor is equal to destination factor for both rgb abd * - NOT source factor is equal to destination factor for both rgb abd
* alpha (which would effectively that mean alpha is not separate) * alpha (which would effectively that mean alpha is not separate)
*/ */
bool separate_alpha = co->enable && bool separate_alpha = alpha_enable &&
!(rt0->rgb_src_factor == rt0->alpha_src_factor && !(rt0->rgb_src_factor == rt0->alpha_src_factor &&
rt0->rgb_dst_factor == rt0->alpha_dst_factor); rt0->rgb_dst_factor == rt0->alpha_dst_factor);
if (co->enable) { if (alpha_enable) {
co->PE_ALPHA_CONFIG = co->PE_ALPHA_CONFIG =
VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR | VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR |
COND(separate_alpha, VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA) | COND(separate_alpha, VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA) |
@@ -77,10 +79,15 @@ etna_blend_state_create(struct pipe_context *pctx,
co->PE_ALPHA_CONFIG = 0; co->PE_ALPHA_CONFIG = 0;
} }
logicop_enable = so->logicop_enable &&
VIV_FEATURE(ctx->screen, chipMinorFeatures2, LOGIC_OP);
co->PE_LOGIC_OP = co->PE_LOGIC_OP =
VIVS_PE_LOGIC_OP_OP(so->logicop_enable ? so->logicop_func : LOGIC_OP_COPY) | VIVS_PE_LOGIC_OP_OP(logicop_enable ? so->logicop_func : LOGIC_OP_COPY) |
0x000E4000 /* ??? */; 0x000E4000 /* ??? */;
co->fo_allowed = !alpha_enable && !logicop_enable;
/* independent_blend_enable not needed: only one rt supported */ /* independent_blend_enable not needed: only one rt supported */
/* XXX alpha_to_coverage / alpha_to_one? */ /* XXX alpha_to_coverage / alpha_to_one? */
/* Set dither registers based on dither status. These registers set the /* Set dither registers based on dither status. These registers set the
@@ -122,7 +129,8 @@ etna_update_blend(struct etna_context *ctx)
* - The color mask is 1111 * - The color mask is 1111
* - No blending is used * - No blending is used
*/ */
bool full_overwrite = (rt0->colormask == 0xf) && !blend->enable; bool full_overwrite = (rt0->colormask == 0xf) &&
blend->fo_allowed;
blend->PE_COLOR_FORMAT = blend->PE_COLOR_FORMAT =
VIVS_PE_COLOR_FORMAT_COMPONENTS(colormask) | VIVS_PE_COLOR_FORMAT_COMPONENTS(colormask) |
COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE); COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE);
src/gallium/drivers/etnaviv/etnaviv_blend.h
+1 -1
View File
@@ -35,7 +35,7 @@ struct etna_context;
struct etna_blend_state { struct etna_blend_state {
struct pipe_blend_state base; struct pipe_blend_state base;
bool enable; bool fo_allowed;
uint32_t PE_ALPHA_CONFIG; uint32_t PE_ALPHA_CONFIG;
uint32_t PE_COLOR_FORMAT; uint32_t PE_COLOR_FORMAT;