From 6a89507be8a94fe258513812b8934d7fe3af462c Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Fri, 4 Aug 2023 14:09:40 -0700 Subject: [PATCH] anv: Program and emit STATE_COMPUTE_MODE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Don't rely on the HW to set values correctly so just emit STATE_COMPUTE_MODE with default values set to zero. Also, this change includes workaround changes:- - 14015808183 (Parent HSD 14015782607) - Need to emit pipe control with HDC flush and untyped cache flush set to 1 when CCS has non-pipelined state update with STATE_COMPUTE_MODE. - 14014427904 (Parent HSD 22013045878) - We need additional invalidate/flush when emitting non-pipelined state commands with multiple CCS enabled. v2: (Tapani) - Use lineage HSD numbers for check - Don't use poisoned WA directly - Use intel_needs_workaround helper Signed-off-by: Sagar Ghuge Reviewed-by: Tapani Pälli Part-of: --- src/intel/vulkan/genX_init_state.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c index 961d252eb8c..c5f98dc351e 100644 --- a/src/intel/vulkan/genX_init_state.c +++ b/src/intel/vulkan/genX_init_state.c @@ -567,6 +567,7 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch) #endif #if GFX_VERx10 >= 125 + anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), zero); anv_batch_emit(&batch, GENX(3DSTATE_MESH_CONTROL), zero); anv_batch_emit(&batch, GENX(3DSTATE_TASK_CONTROL), zero); genX(batch_emit_pipe_control_write)(&batch, device->info, NoWrite, @@ -622,14 +623,26 @@ init_compute_queue_state(struct anv_queue *queue) assert(!queue->device->info->has_aux_map); #endif -#if GFX_VERx10 == 125 - /* Wa_14014427904 - We need additional invalidate/flush when + /* Wa_14015782607 - Issue pipe control with HDC_flush and + * untyped cache flush set to 1 when CCS has NP state update with + * STATE_COMPUTE_MODE. + */ + if (intel_needs_workaround(devinfo, 14015782607) && + queue->family->engine_class == INTEL_ENGINE_CLASS_COMPUTE) { + genX(batch_emit_pipe_control)(&batch, devinfo, + ANV_PIPE_CS_STALL_BIT | + ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT | + ANV_PIPE_HDC_PIPELINE_FLUSH_BIT); + } + +#if GFX_VERx10 >= 125 + /* Wa_14014427904/22013045878 - We need additional invalidate/flush when * emitting NP state commands with ATS-M in compute mode. */ - if (intel_device_info_is_atsm(queue->device->info) && + if (intel_device_info_is_atsm(devinfo) && queue->family->engine_class == INTEL_ENGINE_CLASS_COMPUTE) { genX(batch_emit_pipe_control) - (&batch, queue->device->info, + (&batch, devinfo, ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STATE_CACHE_INVALIDATE_BIT | ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT | @@ -637,7 +650,9 @@ init_compute_queue_state(struct anv_queue *queue) ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | ANV_PIPE_HDC_PIPELINE_FLUSH_BIT); - } + } + + anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), zero); #endif init_common_queue_state(queue, &batch);