diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 41a18f530ff..27e9b3cbd6c 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -555,15 +555,6 @@ void shuffle_from_32bit_read(const brw::fs_builder &bld, uint32_t first_component, uint32_t components); -fs_reg setup_imm_df(const brw::fs_builder &bld, - double v); - -fs_reg setup_imm_b(const brw::fs_builder &bld, - int8_t v); - -fs_reg setup_imm_ub(const brw::fs_builder &bld, - uint8_t v); - enum brw_barycentric_mode brw_barycentric_mode(nir_intrinsic_instr *intr); uint32_t brw_fb_write_msg_control(const fs_inst *inst, diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 2c5c3927124..a6d1a33e498 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -87,6 +87,14 @@ static void fs_nir_emit_global_atomic(nir_to_brw_state &ntb, const fs_builder &bld, nir_intrinsic_instr *instr); +static fs_reg +setup_imm_b(const fs_builder &bld, int8_t v) +{ + const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_B); + bld.MOV(tmp, brw_imm_w(v)); + return tmp; +} + static void fs_nir_setup_outputs(nir_to_brw_state &ntb) { @@ -241,7 +249,6 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) case nir_intrinsic_load_sample_mask_in: assert(s.stage == MESA_SHADER_FRAGMENT); - assert(s.devinfo->ver >= 7); reg = &ntb.system_values[SYSTEM_VALUE_SAMPLE_MASK_IN]; if (reg->file == BAD_FILE) *reg = emit_samplemaskin_setup(ntb); @@ -300,10 +307,6 @@ emit_system_values_block(nir_to_brw_state &ntb, nir_block *block) * a NOT instruction. */ fs_reg inverted = negate(shifted); - if (s.devinfo->ver < 8) { - inverted = abld.vgrf(BRW_REGISTER_TYPE_UW); - abld.NOT(inverted, shifted); - } /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing * with 1 and negating. @@ -404,7 +407,6 @@ fs_nir_emit_cf_list(nir_to_brw_state &ntb, exec_list *list) static void fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) { - const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; bool invert; @@ -418,17 +420,6 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) invert = true; cond_reg = get_nir_src(ntb, cond->src[0].src); cond_reg = offset(cond_reg, bld, cond->src[0].swizzle[0]); - - if (devinfo->ver <= 5 && - (cond->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) { - /* redo boolean resolve on gen5 */ - fs_reg masked = ntb.s.vgrf(glsl_int_type()); - bld.AND(masked, cond_reg, brw_imm_d(1)); - masked.negate = true; - fs_reg tmp = bld.vgrf(cond_reg.type); - bld.MOV(retype(tmp, BRW_REGISTER_TYPE_D), masked); - cond_reg = tmp; - } } else { invert = false; cond_reg = get_nir_src(ntb, if_stmt->condition); @@ -449,16 +440,11 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) } bld.emit(BRW_OPCODE_ENDIF); - - if (devinfo->ver < 7) - ntb.s.limit_dispatch_width(16, "Non-uniform control flow unsupported " - "in SIMD32 mode."); } static void fs_nir_emit_loop(nir_to_brw_state &ntb, nir_loop *loop) { - const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; assert(!nir_loop_has_continue_construct(loop)); @@ -467,10 +453,6 @@ fs_nir_emit_loop(nir_to_brw_state &ntb, nir_loop *loop) fs_nir_emit_cf_list(ntb, &loop->body); bld.emit(BRW_OPCODE_WHILE); - - if (devinfo->ver < 7) - ntb.s.limit_dispatch_width(16, "Non-uniform control flow unsupported " - "in SIMD32 mode."); } static void @@ -611,7 +593,7 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, ntb.bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1), g1, brw_imm_uw(0x3f80)); - } else if (devinfo->ver >= 6) { + } else { /* Bit 15 of g0.0 is 0 if the polygon is front facing. */ fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W)); @@ -632,26 +614,6 @@ optimize_frontfacing_ternary(nir_to_brw_state &ntb, ntb.bld.OR(subscript(tmp, BRW_REGISTER_TYPE_W, 1), g0, brw_imm_uw(0x3f80)); - } else { - /* Bit 31 of g1.6 is 0 if the polygon is front facing. */ - fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D)); - - /* For (gl_FrontFacing ? 1.0 : -1.0), emit: - * - * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D - * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D - * - * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0). - * - * This negation looks like it's safe in practice, because bits 0:4 will - * surely be TRIANGLES - */ - - if (value1 == -1.0f) { - g1_6.negate = true; - } - - ntb.bld.OR(tmp, g1_6, brw_imm_d(0x3f800000)); } ntb.bld.AND(retype(result, BRW_REGISTER_TYPE_D), tmp, brw_imm_d(0xbf800000)); @@ -782,7 +744,7 @@ try_emit_b2fi_of_inot(nir_to_brw_state &ntb, const fs_builder &bld, { const intel_device_info *devinfo = bld.shader->devinfo; - if (devinfo->ver < 6 || devinfo->verx10 >= 125) + if (devinfo->verx10 >= 125) return false; nir_alu_instr *inot_instr = nir_src_as_alu_instr(instr->src[0].src); @@ -915,7 +877,7 @@ emit_fsign(nir_to_brw_state &ntb, const fs_builder &bld, const nir_alu_instr *in */ fs_reg zero = s.vgrf(glsl_double_type()); - bld.MOV(zero, setup_imm_df(bld, 0.0)); + bld.MOV(zero, brw_imm_df(0.0)); bld.CMP(bld.null_reg_df(), op[0], zero, BRW_CONDITIONAL_NZ); bld.MOV(result, zero); @@ -1314,10 +1276,8 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, assert(instr->def.bit_size < 64); fs_reg tmp = bld.vgrf(result.type); - if (devinfo->ver >= 8) { - op[0] = resolve_source_modifiers(bld, op[0]); - op[1] = resolve_source_modifiers(bld, op[1]); - } + op[0] = resolve_source_modifiers(bld, op[0]); + op[1] = resolve_source_modifiers(bld, op[1]); /* AVG(x, y) - ((x ^ y) & 1) */ bld.XOR(tmp, op[0], op[1]); @@ -1370,10 +1330,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, op[1] = subscript(op[1], word_type, 0); - if (devinfo->ver >= 7) - bld.MUL(result, retype(op[0], dword_type), op[1]); - else - bld.MUL(result, op[1], retype(op[0], dword_type)); + bld.MUL(result, retype(op[0], dword_type), op[1]); break; } @@ -1507,82 +1464,76 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, break; } - case nir_op_inot: - if (devinfo->ver >= 8) { - nir_alu_instr *inot_src_instr = nir_src_as_alu_instr(instr->src[0].src); + case nir_op_inot: { + nir_alu_instr *inot_src_instr = nir_src_as_alu_instr(instr->src[0].src); - if (inot_src_instr != NULL && - (inot_src_instr->op == nir_op_ior || - inot_src_instr->op == nir_op_ixor || - inot_src_instr->op == nir_op_iand)) { - /* The sources of the source logical instruction are now the - * sources of the instruction that will be generated. - */ - prepare_alu_destination_and_sources(ntb, bld, inot_src_instr, op, false); - resolve_inot_sources(ntb, bld, inot_src_instr, op); + if (inot_src_instr != NULL && + (inot_src_instr->op == nir_op_ior || + inot_src_instr->op == nir_op_ixor || + inot_src_instr->op == nir_op_iand)) { + /* The sources of the source logical instruction are now the + * sources of the instruction that will be generated. + */ + prepare_alu_destination_and_sources(ntb, bld, inot_src_instr, op, false); + resolve_inot_sources(ntb, bld, inot_src_instr, op); - /* Smash all of the sources and destination to be signed. This - * doesn't matter for the operation of the instruction, but cmod - * propagation fails on unsigned sources with negation (due to - * fs_inst::can_do_cmod returning false). - */ - result.type = - brw_type_for_nir_type(devinfo, - (nir_alu_type)(nir_type_int | - instr->def.bit_size)); - op[0].type = - brw_type_for_nir_type(devinfo, - (nir_alu_type)(nir_type_int | - nir_src_bit_size(inot_src_instr->src[0].src))); - op[1].type = - brw_type_for_nir_type(devinfo, - (nir_alu_type)(nir_type_int | - nir_src_bit_size(inot_src_instr->src[1].src))); + /* Smash all of the sources and destination to be signed. This + * doesn't matter for the operation of the instruction, but cmod + * propagation fails on unsigned sources with negation (due to + * fs_inst::can_do_cmod returning false). + */ + result.type = + brw_type_for_nir_type(devinfo, + (nir_alu_type)(nir_type_int | + instr->def.bit_size)); + op[0].type = + brw_type_for_nir_type(devinfo, + (nir_alu_type)(nir_type_int | + nir_src_bit_size(inot_src_instr->src[0].src))); + op[1].type = + brw_type_for_nir_type(devinfo, + (nir_alu_type)(nir_type_int | + nir_src_bit_size(inot_src_instr->src[1].src))); - /* For XOR, only invert one of the sources. Arbitrarily choose - * the first source. - */ - op[0].negate = !op[0].negate; - if (inot_src_instr->op != nir_op_ixor) - op[1].negate = !op[1].negate; + /* For XOR, only invert one of the sources. Arbitrarily choose + * the first source. + */ + op[0].negate = !op[0].negate; + if (inot_src_instr->op != nir_op_ixor) + op[1].negate = !op[1].negate; - switch (inot_src_instr->op) { - case nir_op_ior: - bld.AND(result, op[0], op[1]); - return; + switch (inot_src_instr->op) { + case nir_op_ior: + bld.AND(result, op[0], op[1]); + return; - case nir_op_iand: - bld.OR(result, op[0], op[1]); - return; + case nir_op_iand: + bld.OR(result, op[0], op[1]); + return; - case nir_op_ixor: - bld.XOR(result, op[0], op[1]); - return; + case nir_op_ixor: + bld.XOR(result, op[0], op[1]); + return; - default: - unreachable("impossible opcode"); - } + default: + unreachable("impossible opcode"); } - op[0] = resolve_source_modifiers(bld, op[0]); } + op[0] = resolve_source_modifiers(bld, op[0]); bld.NOT(result, op[0]); break; + } + case nir_op_ixor: - if (devinfo->ver >= 8) { - resolve_inot_sources(ntb, bld, instr, op); - } + resolve_inot_sources(ntb, bld, instr, op); bld.XOR(result, op[0], op[1]); break; case nir_op_ior: - if (devinfo->ver >= 8) { - resolve_inot_sources(ntb, bld, instr, op); - } + resolve_inot_sources(ntb, bld, instr, op); bld.OR(result, op[0], op[1]); break; case nir_op_iand: - if (devinfo->ver >= 8) { - resolve_inot_sources(ntb, bld, instr, op); - } + resolve_inot_sources(ntb, bld, instr, op); bld.AND(result, op[0], op[1]); break; @@ -1616,12 +1567,6 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_ftrunc: inst = bld.RNDZ(result, op[0]); - if (devinfo->ver < 6) { - set_condmod(BRW_CONDITIONAL_R, inst); - set_predicate(BRW_PREDICATE_NORMAL, - bld.ADD(result, result, brw_imm_f(1.0f))); - inst = bld.MOV(result, result); /* for potential saturation */ - } break; case nir_op_fceil: { @@ -1640,12 +1585,6 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, break; case nir_op_fround_even: inst = bld.RNDE(result, op[0]); - if (devinfo->ver < 6) { - set_condmod(BRW_CONDITIONAL_R, inst); - set_predicate(BRW_PREDICATE_NORMAL, - bld.ADD(result, result, brw_imm_f(1.0f))); - inst = bld.MOV(result, result); /* for potential saturation */ - } break; case nir_op_fquantize2f16: { @@ -1764,7 +1703,6 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_ifind_msb: { assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); - assert(devinfo->ver >= 7); bld.FBH(retype(result, BRW_REGISTER_TYPE_UD), op[0]); @@ -1784,7 +1722,6 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, case nir_op_find_lsb: assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); - assert(devinfo->ver >= 7); bld.FBL(result, op[0]); break; @@ -1979,18 +1916,6 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, default: unreachable("unhandled instruction"); } - - /* If we need to do a boolean resolve, replace the result with -(x & 1) - * to sign extend the low bit to 0/~0 - */ - if (devinfo->ver <= 5 && - !result.is_null() && - (instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) { - fs_reg masked = s.vgrf(glsl_int_type()); - bld.AND(masked, result, brw_imm_d(1)); - masked.negate = true; - bld.MOV(retype(result, BRW_REGISTER_TYPE_D), masked); - } } static void @@ -2021,11 +1946,10 @@ fs_nir_emit_load_const(nir_to_brw_state &ntb, break; case 64: - assert(devinfo->ver >= 7); if (!devinfo->has_64bit_int) { for (unsigned i = 0; i < instr->def.num_components; i++) { bld.MOV(retype(offset(reg, bld, i), BRW_REGISTER_TYPE_DF), - setup_imm_df(bld, instr->value[i].f64)); + brw_imm_df(instr->value[i].f64)); } } else { for (unsigned i = 0; i < instr->def.num_components; i++) @@ -2064,8 +1988,6 @@ get_resource_nir_src(nir_to_brw_state &ntb, const nir_src &src) static fs_reg get_nir_src(nir_to_brw_state &ntb, const nir_src &src) { - const intel_device_info *devinfo = ntb.devinfo; - nir_intrinsic_instr *load_reg = nir_load_reg_for_def(src.ssa); fs_reg reg; @@ -2086,17 +2008,12 @@ get_nir_src(nir_to_brw_state &ntb, const nir_src &src) reg = ntb.ssa_values[decl_reg->def.index]; } - if (nir_src_bit_size(src) == 64 && devinfo->ver == 7) { - /* The only 64-bit type available on gfx7 is DF, so use that. */ - reg.type = BRW_REGISTER_TYPE_DF; - } else { - /* To avoid floating-point denorm flushing problems, set the type by - * default to an integer type - instructions that need floating point - * semantics will set this to F if they need to - */ - reg.type = brw_reg_type_from_bit_size(nir_src_bit_size(src), - BRW_REGISTER_TYPE_D); - } + /* To avoid floating-point denorm flushing problems, set the type by + * default to an integer type - instructions that need floating point + * semantics will set this to F if they need to + */ + reg.type = brw_reg_type_from_bit_size(nir_src_bit_size(src), + BRW_REGISTER_TYPE_D); return reg; } @@ -2520,7 +2437,6 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, unsigned num_components, unsigned first_component) { - const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; fs_visitor &s = ntb.s; @@ -2591,7 +2507,6 @@ emit_gs_input_load(nir_to_brw_state &ntb, const fs_reg &dst, if (nir_src_is_const(vertex_src)) { unsigned vertex = nir_src_as_uint(vertex_src); - assert(devinfo->ver >= 9 || vertex <= 5); bld.MOV(icp_handle, component(start, vertex)); } else { /* The vertex index is non-constant. We need to use indirect @@ -3381,7 +3296,7 @@ fetch_render_target_array_index(const fs_builder &bld) bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 3), brw_imm_uw(0x7ff)); return idx; - } else if (bld.shader->devinfo->ver >= 6) { + } else { /* The render target array index is provided in the thread payload as * bits 26:16 of r0.0. */ @@ -3389,11 +3304,6 @@ fetch_render_target_array_index(const fs_builder &bld) bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 0, 1), brw_imm_uw(0x7ff)); return idx; - } else { - /* Pre-SNB we only ever render into the first layer of the framebuffer - * since layered rendering is not implemented. - */ - return brw_imm_ud(0); } } @@ -3479,10 +3389,8 @@ emit_non_coherent_fb_read(nir_to_brw_state &ntb, const fs_builder &bld, const fs */ if (devinfo->verx10 >= 125) op = SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL; - else if (devinfo->ver >= 9) - op = SHADER_OPCODE_TXF_CMS_W_LOGICAL; else - op = SHADER_OPCODE_TXF_CMS_LOGICAL; + op = SHADER_OPCODE_TXF_CMS_W_LOGICAL; } else { op = SHADER_OPCODE_TXF_LOGICAL; } @@ -3512,7 +3420,6 @@ emit_non_coherent_fb_read(nir_to_brw_state &ntb, const fs_builder &bld, const fs static fs_inst * emit_coherent_fb_read(const fs_builder &bld, const fs_reg &dst, unsigned target) { - assert(bld.shader->devinfo->ver >= 9); fs_inst *inst = bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst); inst->target = target; inst->size_written = 4 * inst->dst.component_size(inst->exec_size); @@ -3604,7 +3511,6 @@ emit_is_helper_invocation(nir_to_brw_state &ntb, fs_reg result) static void emit_fragcoord_interpolation(nir_to_brw_state &ntb, fs_reg wpos) { - const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; fs_visitor &s = ntb.s; @@ -3619,13 +3525,7 @@ emit_fragcoord_interpolation(nir_to_brw_state &ntb, fs_reg wpos) wpos = offset(wpos, bld, 1); /* gl_FragCoord.z */ - if (devinfo->ver >= 6) { - bld.MOV(wpos, s.pixel_z); - } else { - bld.emit(FS_OPCODE_LINTERP, wpos, - s.delta_xy[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL], - s.interp_reg(bld, VARYING_SLOT_POS, 2, 0)); - } + bld.MOV(wpos, s.pixel_z); wpos = offset(wpos, bld, 1); /* gl_FragCoord.w: Already set up in emit_interpolation */ @@ -3683,7 +3583,7 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_W); bld.ASR(tmp, g1, brw_imm_d(15)); bld.NOT(ff, tmp); - } else if (devinfo->ver >= 6) { + } else { /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create * a boolean result from this (~0/true or 0/false). * @@ -3699,21 +3599,6 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) g0.negate = true; bld.ASR(ff, g0, brw_imm_d(15)); - } else { - /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create - * a boolean result from this (1/true or 0/false). - * - * Like in the above case, since the bit is the MSB of g1.6:UD we can use - * the negation source modifier to flip it. Unfortunately the SHR - * instruction only operates on UD (or D with an abs source modifier) - * sources without negation. - * - * Instead, use ASR (which will give ~0/true or 0/false). - */ - fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D)); - g1_6.negate = true; - - bld.ASR(ff, g1_6, brw_imm_d(31)); } return ff; @@ -3722,13 +3607,11 @@ emit_frontfacing_interpolation(nir_to_brw_state &ntb) static fs_reg emit_samplepos_setup(nir_to_brw_state &ntb) { - const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); - assert(devinfo->ver >= 6); const fs_builder abld = bld.annotate("compute sample position"); fs_reg pos = abld.vgrf(BRW_REGISTER_TYPE_F, 2); @@ -3791,106 +3674,57 @@ emit_sampleid_setup(nir_to_brw_state &ntb) assert(s.stage == MESA_SHADER_FRAGMENT); ASSERTED brw_wm_prog_key *key = (brw_wm_prog_key*) s.key; struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); - assert(devinfo->ver >= 6); const fs_builder abld = bld.annotate("compute sample id"); fs_reg sample_id = abld.vgrf(BRW_REGISTER_TYPE_UD); assert(key->multisample_fbo != BRW_NEVER); - if (devinfo->ver >= 8) { - /* Sample ID comes in as 4-bit numbers in g1.0: - * - * 15:12 Slot 3 SampleID (only used in SIMD16) - * 11:8 Slot 2 SampleID (only used in SIMD16) - * 7:4 Slot 1 SampleID - * 3:0 Slot 0 SampleID - * - * Each slot corresponds to four channels, so we want to replicate each - * half-byte value to 4 channels in a row: - * - * dst+0: .7 .6 .5 .4 .3 .2 .1 .0 - * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0 - * - * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16) - * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8 - * - * First, we read g1.0 with a <1,8,0>UB region, causing the first 8 - * channels to read the first byte (7:0), and the second group of 8 - * channels to read the second byte (15:8). Then, we shift right by - * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3 - * values into place. Finally, we AND with 0xf to keep the low nibble. - * - * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V - * and(16) dst<1>D tmp<8,8,1>W 0xf:W - * - * TODO: These payload bits exist on Gfx7 too, but they appear to always - * be zero, so this code fails to work. We should find out why. + /* Sample ID comes in as 4-bit numbers in g1.0: + * + * 15:12 Slot 3 SampleID (only used in SIMD16) + * 11:8 Slot 2 SampleID (only used in SIMD16) + * 7:4 Slot 1 SampleID + * 3:0 Slot 0 SampleID + * + * Each slot corresponds to four channels, so we want to replicate each + * half-byte value to 4 channels in a row: + * + * dst+0: .7 .6 .5 .4 .3 .2 .1 .0 + * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0 + * + * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16) + * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8 + * + * First, we read g1.0 with a <1,8,0>UB region, causing the first 8 + * channels to read the first byte (7:0), and the second group of 8 + * channels to read the second byte (15:8). Then, we shift right by + * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3 + * values into place. Finally, we AND with 0xf to keep the low nibble. + * + * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V + * and(16) dst<1>D tmp<8,8,1>W 0xf:W + * + * TODO: These payload bits exist on Gfx7 too, but they appear to always + * be zero, so this code fails to work. We should find out why. + */ + const fs_reg tmp = abld.vgrf(BRW_REGISTER_TYPE_UW); + + for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { + const fs_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); + /* According to the "PS Thread Payload for Normal Dispatch" + * pages on the BSpec, the sample ids are stored in R0.8/R1.8 + * on gfx20+ and in R1.0/R2.0 on gfx8+. */ - const fs_reg tmp = abld.vgrf(BRW_REGISTER_TYPE_UW); - - for (unsigned i = 0; i < DIV_ROUND_UP(s.dispatch_width, 16); i++) { - const fs_builder hbld = abld.group(MIN2(16, s.dispatch_width), i); - /* According to the "PS Thread Payload for Normal Dispatch" - * pages on the BSpec, the sample ids are stored in R0.8/R1.8 - * on gfx20+ and in R1.0/R2.0 on gfx8+. - */ - const struct brw_reg id_reg = devinfo->ver >= 20 ? xe2_vec1_grf(i, 8) : - brw_vec1_grf(i + 1, 0); - hbld.SHR(offset(tmp, hbld, i), - stride(retype(id_reg, BRW_REGISTER_TYPE_UB), 1, 8, 0), - brw_imm_v(0x44440000)); - } - - abld.AND(sample_id, tmp, brw_imm_w(0xf)); - } else { - const fs_reg t1 = component(abld.vgrf(BRW_REGISTER_TYPE_UD), 0); - const fs_reg t2 = abld.vgrf(BRW_REGISTER_TYPE_UW); - - /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with - * 8x multisampling, subspan 0 will represent sample N (where N - * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or - * 7. We can find the value of N by looking at R0.0 bits 7:6 - * ("Starting Sample Pair Index (SSPI)") and multiplying by two - * (since samples are always delivered in pairs). That is, we - * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then - * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in - * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, - * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by - * populating a temporary variable with the sequence (0, 1, 2, 3), - * and then reading from it using vstride=1, width=4, hstride=0. - * These computations hold good for 4x multisampling as well. - * - * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1): - * the first four slots are sample 0 of subspan 0; the next four - * are sample 1 of subspan 0; the third group is sample 0 of - * subspan 1, and finally sample 1 of subspan 1. - */ - - /* SKL+ has an extra bit for the Starting Sample Pair Index to - * accommodate 16x MSAA. - */ - abld.exec_all().group(1, 0) - .AND(t1, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)), - brw_imm_ud(0xc0)); - abld.exec_all().group(1, 0).SHR(t1, t1, brw_imm_d(5)); - - /* This works for SIMD8-SIMD16. It also works for SIMD32 but only if we - * can assume 4x MSAA. Disallow it on IVB+ - * - * FINISHME: One day, we could come up with a way to do this that - * actually works on gfx7. - */ - if (devinfo->ver >= 7) - s.limit_dispatch_width(16, "gl_SampleId is unsupported in SIMD32 on gfx7"); - abld.exec_all().group(8, 0).MOV(t2, brw_imm_v(0x32103210)); - - /* This special instruction takes care of setting vstride=1, - * width=4, hstride=0 of t2 during an ADD instruction. - */ - abld.emit(FS_OPCODE_SET_SAMPLE_ID, sample_id, t1, t2); + const struct brw_reg id_reg = devinfo->ver >= 20 ? xe2_vec1_grf(i, 8) : + brw_vec1_grf(i + 1, 0); + hbld.SHR(offset(tmp, hbld, i), + stride(retype(id_reg, BRW_REGISTER_TYPE_UB), 1, 8, 0), + brw_imm_v(0x44440000)); } + abld.AND(sample_id, tmp, brw_imm_w(0xf)); + if (key->multisample_fbo == BRW_SOMETIMES) { check_dynamic_msaa_flag(abld, wm_prog_data, INTEL_MSAA_FLAG_MULTISAMPLE_FBO); @@ -3904,13 +3738,11 @@ emit_sampleid_setup(nir_to_brw_state &ntb) static fs_reg emit_samplemaskin_setup(nir_to_brw_state &ntb) { - const intel_device_info *devinfo = ntb.devinfo; const fs_builder &bld = ntb.bld; fs_visitor &s = ntb.s; assert(s.stage == MESA_SHADER_FRAGMENT); struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data); - assert(devinfo->ver >= 6); /* The HW doesn't provide us with expected values. */ assert(wm_prog_data->coarse_pixel_dispatch != BRW_ALWAYS); @@ -4108,14 +3940,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, nir_alu_instr *alu = nir_src_as_alu_instr(instr->src[0]); if (alu != NULL && - alu->op != nir_op_bcsel && - (devinfo->ver > 5 || - (alu->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) != BRW_NIR_BOOLEAN_NEEDS_RESOLVE || - alu->op == nir_op_fneu32 || alu->op == nir_op_feq32 || - alu->op == nir_op_flt32 || alu->op == nir_op_fge32 || - alu->op == nir_op_ine32 || alu->op == nir_op_ieq32 || - alu->op == nir_op_ilt32 || alu->op == nir_op_ige32 || - alu->op == nir_op_ult32 || alu->op == nir_op_uge32)) { + alu->op != nir_op_bcsel) { /* Re-emit the instruction that generated the Boolean value, but * do not store it. Since this instruction will be conditional, * other instructions that want to use the real Boolean value may @@ -4174,10 +3999,6 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, jump->predicate = (devinfo->ver >= 20 ? XE2_PREDICATE_ANY : BRW_PREDICATE_ALIGN1_ANY4H); } - - if (devinfo->ver < 7) - s.limit_dispatch_width( - 16, "Fragment discard/demote not implemented in SIMD32 mode.\n"); break; } @@ -4370,8 +4191,6 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, nir_intrinsic_instr *bary_intrinsic = nir_instr_as_intrinsic(instr->src[0].ssa->parent_instr); nir_intrinsic_op bary_intrin = bary_intrinsic->intrinsic; - enum glsl_interp_mode interp_mode = - (enum glsl_interp_mode) nir_intrinsic_interp_mode(bary_intrinsic); fs_reg dst_xy; if (bary_intrin == nir_intrinsic_load_barycentric_at_offset || @@ -4391,13 +4210,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, interp.type = BRW_REGISTER_TYPE_F; dest.type = BRW_REGISTER_TYPE_F; - if (devinfo->ver < 6 && interp_mode == INTERP_MODE_SMOOTH) { - fs_reg tmp = s.vgrf(glsl_float_type()); - bld.emit(FS_OPCODE_LINTERP, tmp, dst_xy, interp); - bld.MUL(offset(dest, bld, i), tmp, s.pixel_w); - } else { - bld.emit(FS_OPCODE_LINTERP, offset(dest, bld, i), dst_xy, interp); - } + bld.emit(FS_OPCODE_LINTERP, offset(dest, bld, i), dst_xy, interp); } break; } @@ -4492,8 +4305,6 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, break; case nir_intrinsic_load_shared: { - assert(devinfo->ver >= 7); - const unsigned bit_size = instr->def.bit_size; fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM); @@ -4538,8 +4349,6 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_store_shared: { - assert(devinfo->ver >= 7); - const unsigned bit_size = nir_src_bit_size(instr->src[0]); fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX7_BTI_SLM); @@ -4738,7 +4547,7 @@ brw_nir_reduction_op_identity(const fs_builder &bld, return retype(brw_imm_ud(value.u32), type); case 8: if (type == BRW_REGISTER_TYPE_DF) - return setup_imm_df(bld, value.f64); + return brw_imm_df(value.f64); else return retype(brw_imm_u64(value.u64), type); default: @@ -5153,9 +4962,6 @@ static fs_reg get_timestamp(const fs_builder &bld) { fs_visitor &s = *bld.shader; - const intel_device_info *devinfo = s.devinfo; - - assert(devinfo->ver >= 7); fs_reg ts = fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE, BRW_ARF_TIMESTAMP, @@ -6280,16 +6086,9 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, GFX7_BTI_SLM); } } else { - /* Prior to Icelake, they're all lumped into a single cache except on - * Ivy Bridge and Bay Trail where typed messages actually go through - * the render cache. There, we need both fences because we may - * access storage images as either typed or untyped. - */ - const bool render_fence = tgm_fence && devinfo->verx10 == 70; - /* Simulation also complains on Gfx9 if we do not enable commit. */ - const bool commit_enable = render_fence || + const bool commit_enable = instr->intrinsic == nir_intrinsic_end_invocation_interlock || devinfo->ver == 9; @@ -6298,12 +6097,6 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, emit_fence(ubld, opcode, GFX7_SFID_DATAPORT_DATA_CACHE, 0, commit_enable, 0 /* BTI */); } - - if (render_fence) { - fence_regs[fence_regs_count++] = - emit_fence(ubld, opcode, GFX6_SFID_DATAPORT_RENDER_CACHE, 0, - commit_enable, /* bti */ 0); - } } assert(fence_regs_count <= ARRAY_SIZE(fence_regs)); @@ -6405,8 +6198,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, unsigned read_size = nir_intrinsic_range(instr) - (instr->num_components - 1) * type_sz(dest.type); - bool supports_64bit_indirects = - devinfo->platform != INTEL_PLATFORM_CHV && !intel_device_info_is_9lp(devinfo); + bool supports_64bit_indirects = !intel_device_info_is_9lp(devinfo); if (type_sz(dest.type) != 8 || supports_64bit_indirects) { for (unsigned j = 0; j < instr->num_components; j++) { @@ -6594,8 +6386,6 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_load_global: case nir_intrinsic_load_global_constant: { - assert(devinfo->ver >= 8); - assert(instr->def.bit_size <= 32); assert(nir_intrinsic_align(instr) > 0); fs_reg srcs[A64_LOGICAL_NUM_SRCS]; @@ -6630,8 +6420,6 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_store_global: { - assert(devinfo->ver >= 8); - assert(nir_src_bit_size(instr->src[0]) <= 32); assert(nir_intrinsic_write_mask(instr) == (1u << instr->num_components) - 1); @@ -6779,8 +6567,6 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_load_ssbo: { - assert(devinfo->ver >= 7); - const unsigned bit_size = instr->def.bit_size; fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[get_nir_src_bindless(ntb, instr->src[0]) ? @@ -6818,8 +6604,6 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_store_ssbo: { - assert(devinfo->ver >= 7); - const unsigned bit_size = nir_src_bit_size(instr->src[0]); fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; srcs[get_nir_src_bindless(ntb, instr->src[1]) ? @@ -7008,8 +6792,6 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_load_scratch: { - assert(devinfo->ver >= 7); - assert(instr->def.num_components == 1); const unsigned bit_size = instr->def.bit_size; fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; @@ -7021,11 +6803,9 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, brw_imm_ud(INTEL_MASK(31, 10))); srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS); srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle; - } else if (devinfo->ver >= 8) { + } else { srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX8_BTI_STATELESS_NON_COHERENT); - } else { - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(BRW_BTI_STATELESS); } srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); @@ -7075,8 +6855,6 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, } case nir_intrinsic_store_scratch: { - assert(devinfo->ver >= 7); - assert(nir_src_num_components(instr->src[0]) == 1); const unsigned bit_size = nir_src_bit_size(instr->src[0]); fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS]; @@ -7088,11 +6866,9 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, brw_imm_ud(INTEL_MASK(31, 10))); srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX125_NON_BINDLESS); srcs[SURFACE_LOGICAL_SRC_SURFACE_HANDLE] = handle; - } else if (devinfo->ver >= 8) { + } else { srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GFX8_BTI_STATELESS_NON_COHERENT); - } else { - srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(BRW_BTI_STATELESS); } srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1); @@ -7377,29 +7153,17 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, case nir_intrinsic_quad_swap_horizontal: { const fs_reg value = get_nir_src(ntb, instr->src[0]); const fs_reg tmp = bld.vgrf(value.type); - if (devinfo->ver <= 7) { - /* The hardware doesn't seem to support these crazy regions with - * compressed instructions on gfx7 and earlier so we fall back to - * using quad swizzles. Fortunately, we don't support 64-bit - * anything in Vulkan on gfx7. - */ - assert(nir_src_bit_size(instr->src[0]) == 32); - const fs_builder ubld = bld.exec_all(); - ubld.emit(SHADER_OPCODE_QUAD_SWIZZLE, tmp, value, - brw_imm_ud(BRW_SWIZZLE4(1,0,3,2))); - bld.MOV(retype(dest, value.type), tmp); - } else { - const fs_builder ubld = bld.exec_all().group(s.dispatch_width / 2, 0); - const fs_reg src_left = horiz_stride(value, 2); - const fs_reg src_right = horiz_stride(horiz_offset(value, 1), 2); - const fs_reg tmp_left = horiz_stride(tmp, 2); - const fs_reg tmp_right = horiz_stride(horiz_offset(tmp, 1), 2); + const fs_builder ubld = bld.exec_all().group(s.dispatch_width / 2, 0); - ubld.MOV(tmp_left, src_right); - ubld.MOV(tmp_right, src_left); + const fs_reg src_left = horiz_stride(value, 2); + const fs_reg src_right = horiz_stride(horiz_offset(value, 1), 2); + const fs_reg tmp_left = horiz_stride(tmp, 2); + const fs_reg tmp_right = horiz_stride(horiz_offset(tmp, 1), 2); + + ubld.MOV(tmp_left, src_right); + ubld.MOV(tmp_right, src_left); - } bld.MOV(retype(dest, value.type), tmp); break; } @@ -8264,15 +8028,11 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, if (srcs[TEX_LOGICAL_SRC_MCS].file == BAD_FILE && (instr->op == nir_texop_txf_ms || instr->op == nir_texop_samples_identical)) { - if (devinfo->ver >= 7) { - srcs[TEX_LOGICAL_SRC_MCS] = - emit_mcs_fetch(ntb, srcs[TEX_LOGICAL_SRC_COORDINATE], - instr->coord_components, - srcs[TEX_LOGICAL_SRC_SURFACE], - srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE]); - } else { - srcs[TEX_LOGICAL_SRC_MCS] = brw_imm_ud(0u); - } + srcs[TEX_LOGICAL_SRC_MCS] = + emit_mcs_fetch(ntb, srcs[TEX_LOGICAL_SRC_COORDINATE], + instr->coord_components, + srcs[TEX_LOGICAL_SRC_SURFACE], + srcs[TEX_LOGICAL_SRC_SURFACE_HANDLE]); } srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(instr->coord_components); @@ -8303,10 +8063,8 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, */ if (devinfo->verx10 >= 125) opcode = SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL; - else if (devinfo->ver >= 9) - opcode = SHADER_OPCODE_TXF_CMS_W_LOGICAL; else - opcode = SHADER_OPCODE_TXF_CMS_LOGICAL; + opcode = SHADER_OPCODE_TXF_CMS_W_LOGICAL; break; case nir_texop_txf_ms_mcs_intel: opcode = SHADER_OPCODE_TXF_MCS_LOGICAL; @@ -8360,14 +8118,11 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, */ if (srcs[TEX_LOGICAL_SRC_MCS].file == BRW_IMMEDIATE_VALUE) { bld.MOV(dst, brw_imm_ud(0u)); - } else if (devinfo->ver >= 9) { + } else { fs_reg tmp = s.vgrf(glsl_uint_type()); bld.OR(tmp, srcs[TEX_LOGICAL_SRC_MCS], offset(srcs[TEX_LOGICAL_SRC_MCS], bld, 1)); bld.CMP(dst, tmp, brw_imm_ud(0u), BRW_CONDITIONAL_EQ); - } else { - bld.CMP(dst, srcs[TEX_LOGICAL_SRC_MCS], brw_imm_ud(0u), - BRW_CONDITIONAL_EQ); } return; } @@ -8394,8 +8149,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, inst->has_packed_lod_ai_src = pack_lod_and_array_index; const unsigned dest_size = nir_tex_instr_dest_size(instr); - if (devinfo->ver >= 9 && - instr->op != nir_texop_tg4 && instr->op != nir_texop_query_levels) { + if (instr->op != nir_texop_tg4 && instr->op != nir_texop_query_levels) { unsigned write_mask = nir_def_components_read(&instr->def); assert(write_mask != 0); /* dead code should have been eliminated */ if (instr->is_sparse) { @@ -8436,7 +8190,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, if (instr->op == nir_texop_query_levels) { /* # levels is in .w */ - if (devinfo->ver <= 9) { + if (devinfo->ver == 9) { /** * Wa_1940217: * @@ -8451,12 +8205,6 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, } else { nir_dest[0] = offset(dst, bld, 3); } - } else if (instr->op == nir_texop_txs && - dest_size >= 3 && devinfo->ver < 7) { - /* Gfx4-6 return 0 instead of 1 for single layer surfaces. */ - fs_reg depth = offset(dst, bld, 2); - nir_dest[2] = s.vgrf(glsl_int_type()); - bld.emit_minmax(nir_dest[2], depth, brw_imm_d(1), BRW_CONDITIONAL_GE); } /* The residency bits are only in the first component. */ @@ -8607,70 +8355,6 @@ shuffle_from_32bit_read(const fs_builder &bld, shuffle_src_to_dst(bld, dst, src, first_component, components); } -fs_reg -setup_imm_df(const fs_builder &bld, double v) -{ - const struct intel_device_info *devinfo = bld.shader->devinfo; - assert(devinfo->ver >= 7); - - if (devinfo->ver >= 8) - return brw_imm_df(v); - - /* gfx7.5 does not support DF immediates straightforward but the DIM - * instruction allows to set the 64-bit immediate value. - */ - if (devinfo->platform == INTEL_PLATFORM_HSW) { - const fs_builder ubld = bld.exec_all().group(1, 0); - fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_DF, 1); - ubld.DIM(dst, brw_imm_df(v)); - return component(dst, 0); - } - - /* gfx7 does not support DF immediates, so we generate a 64-bit constant by - * writing the low 32-bit of the constant to suboffset 0 of a VGRF and - * the high 32-bit to suboffset 4 and then applying a stride of 0. - * - * Alternatively, we could also produce a normal VGRF (without stride 0) - * by writing to all the channels in the VGRF, however, that would hit the - * gfx7 bug where we have to split writes that span more than 1 register - * into instructions with a width of 4 (otherwise the write to the second - * register written runs into an execmask hardware bug) which isn't very - * nice. - */ - union { - double d; - struct { - uint32_t i1; - uint32_t i2; - }; - } di; - - di.d = v; - - const fs_builder ubld = bld.exec_all().group(1, 0); - const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2); - ubld.MOV(tmp, brw_imm_ud(di.i1)); - ubld.MOV(horiz_offset(tmp, 1), brw_imm_ud(di.i2)); - - return component(retype(tmp, BRW_REGISTER_TYPE_DF), 0); -} - -fs_reg -setup_imm_b(const fs_builder &bld, int8_t v) -{ - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_B); - bld.MOV(tmp, brw_imm_w(v)); - return tmp; -} - -fs_reg -setup_imm_ub(const fs_builder &bld, uint8_t v) -{ - const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UB); - bld.MOV(tmp, brw_imm_uw(v)); - return tmp; -} - static void fs_nir_emit_instr(nir_to_brw_state &ntb, nir_instr *instr) {