From 69c927debeb705ec46b50d8e5ddfacb81264b244 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 25 Nov 2020 19:51:42 -0500 Subject: [PATCH] radeonsi: disable WGP mode on gfx10.3 to prevent hangs I think that reducing the CU mask to 1 disabled CU per SA broke the WGP mode on VanGogh, causing a hang. To be sure, disable it on all chips. Fixes: 9538b9a68ed - radeonsi: add support for Sienna Cichlid Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_state_shaders.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 121360daa89..651dd8c4c29 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -1155,7 +1155,10 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, S_00B228_VGPRS((shader->config.num_vgprs - 1) / (wave_size == 32 ? 8 : 4)) | S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_DX10_CLAMP(1) | - S_00B228_MEM_ORDERED(1) | S_00B228_WGP_MODE(1) | + S_00B228_MEM_ORDERED(1) | + /* Disable the WGP mode on gfx10.3 because it can hang. (it happened on VanGogh) + * Let's disable it on all chips that disable exactly 1 CU per SA for GS. */ + S_00B228_WGP_MODE(sscreen->info.chip_class == GFX10) | S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt)); si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |