From 697e1cdeef351989d5e33094aa5822b554aee564 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Wed, 12 Jan 2022 14:58:32 +0800 Subject: [PATCH] radeonsi: lower nir_intrinsic_is_sparse_texels_resident MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Marek Olšák Signed-off-by: Qiang Yu Part-of: --- src/gallium/drivers/radeonsi/si_shader_nir.c | 30 ++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index cca73be4ad1..f17b4f17fb2 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c @@ -310,6 +310,34 @@ static void si_lower_io(struct nir_shader *nir) } } +static bool +lower_intrinsic_filter(const nir_instr *instr, const void *dummy) +{ + return instr->type == nir_instr_type_intrinsic; +} + +static nir_ssa_def * +lower_intrinsic_instr(nir_builder *b, nir_instr *instr, void *dummy) +{ + nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); + + switch (intrin->intrinsic) { + case nir_intrinsic_is_sparse_texels_resident: + /* code==0 means sparse texels are resident */ + return nir_ieq_imm(b, intrin->src[0].ssa, 0); + default: + return NULL; + } +} + +static bool si_lower_intrinsics(nir_shader *nir) +{ + return nir_shader_lower_instructions(nir, + lower_intrinsic_filter, + lower_intrinsic_instr, + NULL); +} + /** * Perform "lowering" operations on the NIR that are run once when the shader * selector is created. @@ -335,6 +363,8 @@ static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir) }; NIR_PASS_V(nir, nir_lower_image, &lower_image_options); + NIR_PASS_V(nir, si_lower_intrinsics); + const nir_lower_subgroups_options subgroups_options = { .subgroup_size = 64, .ballot_bit_size = 64,