diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 07b2d5d2348..e9036393744 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -136,18 +136,10 @@ gather_intrinsic_store_output_info(const nir_shader *nir, const nir_intrinsic_in { const nir_io_semantics io_sem = nir_intrinsic_io_semantics(instr); const unsigned location = io_sem.location; - const unsigned num_slots = io_sem.num_slots; const unsigned component = nir_intrinsic_component(instr); const unsigned write_mask = nir_intrinsic_write_mask(instr); - uint8_t *output_usage_mask = NULL; switch (nir->info.stage) { - case MESA_SHADER_VERTEX: - output_usage_mask = info->vs.output_usage_mask; - break; - case MESA_SHADER_TESS_EVAL: - output_usage_mask = info->tes.output_usage_mask; - break; case MESA_SHADER_FRAGMENT: if (location >= FRAG_RESULT_DATA0) { const unsigned fs_semantic = location + io_sem.dual_source_blend_index; @@ -161,12 +153,6 @@ gather_intrinsic_store_output_info(const nir_shader *nir, const nir_intrinsic_in break; } - if (output_usage_mask) { - for (unsigned i = 0; i < num_slots; i++) { - output_usage_mask[location + i] |= ((write_mask >> (i * 4)) & 0xf) << component; - } - } - if (consider_force_vrs && location == VARYING_SLOT_POS) { unsigned pos_w_chan = 3 - component; diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h index 256c6a33d8a..8410fba416d 100644 --- a/src/amd/vulkan/radv_shader_info.h +++ b/src/amd/vulkan/radv_shader_info.h @@ -115,7 +115,6 @@ struct radv_shader_info { unsigned nir_shared_size; struct { - uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1]; bool needs_draw_id; bool needs_instance_id; bool as_es; @@ -146,7 +145,6 @@ struct radv_shader_info { bool has_pipeline_stat_query; } gs; struct { - uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1]; bool as_es; enum tess_primitive_mode _primitive_mode; enum gl_tess_spacing spacing;