diff --git a/src/intel/compiler/brw/brw_eu_emit.c b/src/intel/compiler/brw/brw_eu_emit.c
index 27d70b793d8..9122a441f27 100644
--- a/src/intel/compiler/brw/brw_eu_emit.c
+++ b/src/intel/compiler/brw/brw_eu_emit.c
@@ -920,28 +920,7 @@ ALU3(ADD3)
 ALU1(MOV)
 ALU2(MUL)
 ALU2(AVG)
-
-brw_eu_inst *
-brw_ADD(struct brw_codegen *p, struct brw_reg dest,
-        struct brw_reg src0, struct brw_reg src1)
-{
-   /* 6.2.2: add */
-   if (src0.type == BRW_TYPE_F ||
-       (src0.file == IMM &&
-	src0.type == BRW_TYPE_VF)) {
-      assert(src1.type != BRW_TYPE_UD);
-      assert(src1.type != BRW_TYPE_D);
-   }
-
-   if (src1.type == BRW_TYPE_F ||
-       (src1.file == IMM &&
-	src1.type == BRW_TYPE_VF)) {
-      assert(src0.type != BRW_TYPE_UD);
-      assert(src0.type != BRW_TYPE_D);
-   }
-
-   return brw_alu2(p, BRW_OPCODE_ADD, dest, src0, src1);
-}
+ALU2(ADD)
 
 brw_eu_inst *
 brw_LINE(struct brw_codegen *p, struct brw_reg dest,
diff --git a/src/intel/compiler/brw/brw_eu_validate.c b/src/intel/compiler/brw/brw_eu_validate.c
index 265c1dceea0..086c74bdd9f 100644
--- a/src/intel/compiler/brw/brw_eu_validate.c
+++ b/src/intel/compiler/brw/brw_eu_validate.c
@@ -2269,6 +2269,12 @@ instruction_restrictions(const struct brw_isa_info *isa,
                brw_type_size_bytes(inst->src[1].type) > 4,
                "AVG does not support 64-bit types.");
    }
+
+   if (inst->opcode == BRW_OPCODE_ADD) {
+      ERROR_IF(brw_type_is_int(inst->src[0].type) !=
+               brw_type_is_int(inst->src[1].type),
+               "ADD can't mix float and non-float sources.");
+   }
 }
 
 static void
diff --git a/src/intel/compiler/brw/test_eu_validate.cpp b/src/intel/compiler/brw/test_eu_validate.cpp
index 2f2866ae896..c5812265129 100644
--- a/src/intel/compiler/brw/test_eu_validate.cpp
+++ b/src/intel/compiler/brw/test_eu_validate.cpp
@@ -3969,3 +3969,16 @@ TEST_P(validation_test, mul_dont_accept_int_accumulator_src)
    EXPECT_FALSE(validate(p));
    clear_instructions(p);
 }
+
+TEST_P(validation_test, add_dont_mix_integer_and_float_sources)
+{
+   brw_reg a = brw_ud8_grf(10, 0);
+   brw_reg b = brw_ud8_grf(20, 0);
+   brw_reg c = brw_ud8_grf(30, 0);
+
+   brw_ADD(p, retype(a, BRW_TYPE_F),
+              retype(b, BRW_TYPE_F),
+              retype(c, BRW_TYPE_UD));
+   EXPECT_FALSE(validate(p));
+   clear_instructions(p);
+}